公开(公告)号：WO1996037046A1

公开(公告)日：1996-11-21

申请号：PCT/DE1996000858

申请日：1996-05-15

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  DRAXELMAYR, Dieter

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: H03K05/24

CPC classification number: H03F1/083 ,  H03K5/2418

Abstract: In order to reduce the delay between the zero passage of the input voltage and the switching of the output in an analog comparator, a second transistor (T2; T20) controlled by a reference potential (VR1; VR2) is connected with its output circuit between the input and the output of a first transistor (T1) which is controlled by the output of a comparator differential stage. The saturation of said first transistor can be prevented with such a circuit.

Abstract translation: 为了减小过零点输入电压和输出的一个模拟比较器的切换之间的延迟时间，一个从参考电势（VR1，VR2）控制的第二晶体管（T2; T20）（与输入和第一晶体管的输出端之间的输出电路 T1）被连接，它是由比较差动级的输出的控制。 利用这样的电路，能够防止在第一晶体管的饱和度。

公开(公告)号：WO1995003651A1

公开(公告)日：1995-02-02

申请号：PCT/US1994007104

申请日：1994-06-24

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： NATIONAL SEMICONDUCTOR CORPORATION ,  RAPP, A., Karl ,  STOIAN, Lee, L.

IPC: H03K05/24

CPC classification number: H03K5/2418 ,  H03F3/45094 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45508 ,  H03F2203/45656 ,  H03F2203/45658 ,  H03K5/2481

Abstract: A voltage comparator produces a current output as a function of the differential input voltage. Three transfer functions are detailed. In the linear transfer mode the output varies linearly in the transition region and swings between zero and a well-defined current value. In a truncated response mode, the output is zero for zero differential input voltage, remains at zero for one input voltage polarity, and rises for the other polarity input linearly to a well-defined current value. In the folded response mode the output current is zero for zero differential input and rises linearly in the transition region to a well-defined current value for either polarity of differential input. While a CMOS form of construction is preferred, bipolar construction is also shown.

Abstract translation: 电压比较器产生作为差分输入电压的函数的电流输出。 详细介绍三种传递功能。 在线性传输模式下，输出在过渡区域中线性变化，并在零和定义明确的电流值之间摆动。 在截断响应模式下，零差分输入电压的输出为零，对于一个输入电压极性，输出保持为零，另一极性输入线性上升到明确定义的电流值。 在折叠响应模式下，零差分输入的输出电流为零，并且在过渡区域中线性上升到差分输入的任一极性的明确定义的电流值。 虽然优选构造CMOS形式，但是也示出了双极结构。

公开(公告)号：WO2008118824A3

公开(公告)日：2009-05-07

申请号：PCT/US2008057943

申请日：2008-03-21

Applicant: DSM SOLUTIONS INC ,  KAPOOR ASHOK K

Inventor： KAPOOR ASHOK K

IPC: G06F13/40 ,  H01L21/331 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/73 ,  H01L29/808 ,  H03K19/0175

CPC classification number: H01L21/8248 ,  H01L27/0623 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/808 ,  H03K5/2418 ,  H03K19/001 ,  H04L25/0264

Abstract: Integrated circuit systems and semiconductor devices for generating, transmitting, receiving and manipulating clock and/or data signals. Semiconductor device including clock circuit having FETs and clock driver circuit having BJT. System and devices may include translator circuit translating signals with lower voltage swing into signals with higher voltage swing and circuit block operating at higher voltage swing. Wiring networks for communicating signals between individual circuits or system components. Integrated circuit device can include a BJT having first base electrode comprising semiconductor material doped to first conductivity type formed on and in contact with surface of semiconductor substrate and separated from emitter electrode by separation space. First base region can be formed in substrate below emitter electrode and include first portion of substrate doped to first conductivity type. Second base region can be formed in substrate below separation space and can include second portion of substrate doped to first conductivity type.

Abstract translation: 用于生成，发送，接收和操纵时钟和/或数据信号的集成电路系统和半导体器件。 包括具有FET的时钟电路和具有BJT的时钟驱动器电路的半导体器件。 系统和设备可以包括转换器电路将具有较低电压摆幅的信号转换成具有较高电压摆幅的信号，并且在更高的电压摆幅下操作电路块。 用于在各个电路或系统组件之间传送信号的接线网络。 集成电路器件可以包括具有第一基极的BJT，该第一基极包括掺杂到第一导电类型的半导体材料，该半导体材料形成在半导体衬底的表面上并与半导体衬底的表面接触，并且通 第一基区可以形成在发射极电极下方的衬底中，并且包括掺杂到第一导电类型的衬底的第一部分。 第二基区可以形成在分离空间下方的衬底中，并且可以包括掺杂到第一导电类型的衬底的第二部分。

公开(公告)号：WO2006129414A1

公开(公告)日：2006-12-07

申请号：PCT/JP2006/305701

申请日：2006-03-22

Applicant: サンケン電気株式会社 ,  鈴木 弘樹

Inventor： 鈴木 弘樹

IPC: H03K5/08 ,  H03F3/45

CPC classification number: H03K5/2418 ,  H03F3/45085 ,  H03F2200/156 ,  H03F2203/45224 ,  H03F2203/45352 ,  H03F2203/45536

Abstract: 　比較回路の入力端子に負電圧が印加されたときの出力信号の反転を防止する。負電圧が印加される第１の入力端子(5)又は第２の入力端子(6)に接続された一方の主端子及び出力スイッチ(7)の制御端子に接続された他方の主端子を有する補償スイッチ(10)の制御端子をグラウンドに接続することにより、補償スイッチ(10)の何れかの主端子に接続された第１の入力端子(5)又は第２の入力端子(6)に負電圧が印加されたときに、補償スイッチ(10)がオンに切り換えられ、出力スイッチ(7)の制御端子がゼロボルト未満の負電位まで低下するので、出力スイッチ(7)をオフ状態に維持でき、出力スイッチ(7)は誤動作を発生しない。

Abstract translation: 一种比较电路，其中即使当向输入端子施加负电压时，也防止了输出信号的反转。 补偿开关（10）的控制端子，其具有连接到施加负电压的第一输入端子（5）或第二输入端子（6）的一个主端子，并且另一个主端子连接 到输出开关（7）的控制端子连接到接地点，由此当向连接到补偿开关的一个主端子的第一（5）或第二（6）输入端子施加负电压时， （10）时，补偿开关（10）导通，将输出开关（7）的控制端子处的电位降低到零伏特以下，或者降低到负电位。 这可以将输出开关（7）保持在断开状态，从而抑制输出开关（7）的故障。

公开(公告)号：WO0251001A3

公开(公告)日：2003-11-13

申请号：PCT/US0150072

申请日：2001-12-20

Applicant: INTERSIL INC

Inventor： PRENTICE JOHN S

IPC: H03F3/45 ,  H03K5/24

CPC classification number: H03F3/45556 ,  H03F2203/45464 ,  H03F2203/45584 ,  H03F2203/45596 ,  H03K5/2418

Abstract: A bias circuit (101) that provides biasing for a differential circuit (103). The bias circuit (101) includes first and second transistors (Q3, Q4), first and second impedance devices (R1, R2), a reference current source (201) and an amplifier (203). The first and second transistors (Q3, Q4) each have a control input and a current path coupled between a first node (V1) and ground, where the control inputs of the first and second transistors receive the differential signal (VIN). The impedance devices (R1, R2) are each coupled between a control input of one of the first and second transistors and a second node (V2). The reference current source (201) provides a reference current (IREF) for the first node (V1) and the amplifier (203) has an input coupled to the first node (V1) and an output coupled to the second node (V2). The transistors (Q3, Q4), (Q1, Q2) of the bias circuit and the differential circuit, respectively, may be matched, NPN bipolar junction transistors with emitters connected to ground. A filter capacitor (C1) may be coupled between the first node (V1) and ground and operates as a low pass filter.

Abstract translation: 提供用于差分电路（103）的偏置的偏置电路（101）。 偏置电路（101）包括第一和第二晶体管（Q3，Q4），第一和第二阻抗器件（R1，R2），参考电流源（201）和放大器（203）。 第一和第二晶体管（Q3，Q4）各自具有耦合在第一节点（V1）和地之间的控制输入和电流路径，其中第一和第二晶体管的控制输入接收差分信号（VIN）。 阻抗器件（R1，R2）分别耦合在第一和第二晶体管之一的控制输入端和第二节点（V2）之间。 参考电流源（201）为第一节点（V1）提供参考电流（IREF），并且放大器（203）具有耦合到第一节点（V1）的输入和耦合到第二节点（V2）的输出。 偏置电路和差分电路的晶体管（Q3，Q4），（Q1，Q2）分别可以匹配，NPN双极结型晶体管与发射极连接到地。 滤波电容器（C1）可以耦合在第一节点（V1）和地之间，并作为低通滤波器工作。

公开(公告)号：WO01047109A2

公开(公告)日：2001-06-28

申请号：PCT/EP2000/012508

申请日：2000-12-11

IPC: H03F3/45 ,  H03K5/24 ,  H04L25/02 ,  H03K

CPC classification number: H04L25/0292 ,  H03F3/45085 ,  H03F3/45556 ,  H03F3/4556 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45592 ,  H03K5/2418 ,  H04L25/0276 ,  H04L25/028

Abstract: Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits (3 and 5), respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) (1) is applied across a pair of series connected resistors (7 and 9), and to the inputs of the amplifiers (3 and 5). The common mode voltage signal (11) is fed to the inputs of third and fourth amplifiers (15 and 17). The third and fourth amplifiers (15 and 17) ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.

Abstract translation: 使用分别在第一和第二电压子范围内工作的第一和第二放大器电路（3和5）来解决在宽共模电压范围内使用双极性差分电路相关的问题。 低电压差分信号（LVDS）（1）被施加在一对串联连接的电阻（7和9）和放大器（3和5）的输入端。 共模电压信号（11）被馈送到第三和第四放大器（15和17）的输入端。 第三和第四放大器（15和17）确保LVDS接收器在差分输入信号范围和整个共模范围内具有恒定的线性传输特性，特别是在放大器过渡区域。

公开(公告)号：WO1986003012A1

公开(公告)日：1986-05-22

申请号：PCT/JP1985000631

申请日：1985-11-12

Applicant: FANUC LTD ,  ISHIDA, Hiroshi

Inventor： FANUC LTD

IPC: G01R19/165

CPC classification number: G01R19/1658 ,  H03K5/2418

Abstract: Current supply circuits (23), (24) having switching elements are inserted on the power supply side (31) and on the power return wire side (32) of a differential amplifier means (10) in a voltage comparator, and are turned on or off. This makes it possible to obtain a voltage comparator which intermittently operates at high speeds consuming a reduced amount of electric power.

公开(公告)号：WO1984002622A1

公开(公告)日：1984-07-05

申请号：PCT/US1983001658

申请日：1983-10-24

Applicant: MOTOROLA, Inc.

Inventor： MOTOROLA, Inc. ,  JOSEPH, Eric, D.

IPC: H03K05/153

CPC classification number: H03K17/0824 ,  H03K5/2418

Abstract: A comparator circuit (40) which includes a differential pair of transistors (12, 14) forming differential inputs of the comparator and a voltage level shift circuit (24, 26) coupled in series connection path with the emitters of the pair of transistors. The voltage level shift circuit includes an additional (26) transistor having its collector-emitter path connected in series between an output of the comparator and the emitter of the first pair of transistors; a first diode coupled in a series- conduction path to the emitter of the second one of the pair of transistors and having an anode connected to the base of the additional transistor; and a second diode (42) coupled between the base and emitter of the additional transistor wherein the effective beta of the additional transistor is reduced to reduce the bias current that would otherwise flow through the first transistor when such transistor is rendered conductive by an applied differential input signal.