公开(公告)号：WO01076077A2

公开(公告)日：2001-10-11

申请号：PCT/CA2001/000410

申请日：2001-03-30

IPC: H03M13/09 ,  H03M13/15 ,  H04L1/00 ,  H04L1/18

CPC classification number: H04L1/0057 ,  H03M13/09 ,  H03M13/091 ,  H03M13/15 ,  H03M13/6575 ,  H04L1/0043 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/1809 ,  H04L1/1816 ,  H04L1/1835 ,  H04L1/1874

Abstract: Transmitters, receivers, and coding schemes to increase data rate and decrease bit error rate of an optical data link are disclosed. Data is transmitted across the link with a less than nominal bit error rate (BER), by encoding the data using a forward error correction (FEC) code or by requesting retransmission of transmitted packets in error. Data is transmitted at a speed that introduces errors at a rate that is in excess of the nominal BER but that may be corrected using the FEC code or retransmission so that the data may be received with less than the nominal BER. The data rate is increased as the link operating speed is increased beyond the overhead required by the FEC codes or retransmission. High speed FEC encoders and decoders facilitating such transmission are disclosed.

Abstract translation: 公开了用于增加数据速率并降低光数据链路的误码率的发射机，接收机和编码方案。 通过使用前向纠错（FEC）码对数据进行编码或者通过请求错误发送的数据包的重传，通过小于标称误码率（BER）的链路传输数据。 数据以以超过标称BER的速率引入误差的速度发送，但是可以使用FEC码或重传来校正数据，以便可以以小于标称BER的速率接收数据。 数据速率随着链路运行速度增加而超过FEC码或重传所需的开销而增加。 公开了促进这种传输的高速FEC编码器和解码器。

公开(公告)号：WO2016050323A1

公开(公告)日：2016-04-07

申请号：PCT/EP2014/071249

申请日：2014-10-03

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)

Inventor： ASANAKA, Kazunori ,  AALTO, Christer

IPC: H03M13/09

CPC classification number: H03M13/091 ,  H03M13/617

Abstract: The disclosure relates to a method (200) performed in a cyclic redundancy check, CRC, device (300) for calculating, based on a generator polynomial G(x), a CRC code for a message block. The method (200) comprises receiving (201) n segments of the message block in forward order or in reverse order, wherein at least one segment is received in reverse order; calculating (202) for each of the n segments a respective segment CRC code based on the generator polynomial G(x), wherein each segment CRC is calculated according to the received order of the segment; aligning (203) each of the n segment CRC codes; and calculating (204) the CRC code for the message block by adding together each of the aligned n segment CRC codes. The disclosure also relates to a device (300), computer program and computer program product.

Abstract translation: 本发明涉及在循环冗余校验CRC，装置（300）中执行的方法（200），用于基于生成多项式G（x）计算消息块的CRC码。 方法（200）包括以正向或反向顺序接收（201）消息块的n个段，其中以相反的顺序接收至少一个段; 基于生成多项式G（x），对n个段中的每个段计算（202）各个段CRC码，其中根据段的接收顺序来计算每个段CRC; 对准（203）n个区段CRC码中的每一个; 以及通过将对准的n个区段CRC码中的每一个相加来计算（204）消息块的CRC码。 本公开还涉及一种设备（300），计算机程序和计算机程序产品。

公开(公告)号：WO2012136546A1

公开(公告)日：2012-10-11

申请号：PCT/EP2012/055579

申请日：2012-03-29

Applicant: ROBERT BOSCH GMBH ,  HARTWICH, Florian

Inventor： HARTWICH, Florian

IPC: G06F13/42 ,  H04L12/413 ,  G06F11/00

CPC classification number: G06F13/362 ,  G06F13/4282 ,  H03M13/091 ,  H04L1/0061 ,  H04L1/0083 ,  H04L12/4013 ,  H04L12/40169 ,  H04L12/4135 ,  H04L2001/0094 ,  H04L2012/40215

Abstract: Es wird ein Verfahren zur seriellen Datenübertragung in einem Bussystem mit mindestens zweiteilnehmenden Datenverarbeitungseinheiten beschrieben, wobei die Datenverarbeitungseinheiten über den Bus Nachrichten austauschen, wobei die gesendeten Nachrichten einen logischen Aufbau gemäß der CAN- Norm ISO 11898-1 aufweisen,wobei der logische Aufbau ein Start-of-Frame-Bit, ein Arbitration Field, ein Control Field, ein Data Field, ein CRC Field, ein Acknowledge Field und eine End-of-Frame Sequenz umfasst, wobei das Control Field einen Data Length Code umfasst, der eine Information über die Länge des Data Fields enthält. Das CRC Field der übertragenen Nachrichten kann in Abhängigkeit vom Inhalt des Data Length Code wenigstens zwei unterschiedliche Anzahlen von Bits aufweisen.

Abstract translation: 它描述了具有至少两个用于在总线系统中的串行数据传递的方法参与的数据处理单元，其中，经由所述总线消息，其中，发送的所述消息具有根据CAN标准ISO 11898-1，在那里开始的逻辑结构的逻辑结构数据处理单元交换 包括的I-帧位，仲裁字段，控制字段，数据字段，CRC字段，确认字段和帧结束-的序列，其中所述控制字段包括数据长度代码，有关的信息 包含数据字段的长度。 所发送的消息的CRC字段可包括至少部分地基于数据长度代码的内容依赖位中的两个不同的号码。

公开(公告)号：WO2009008682A1

公开(公告)日：2009-01-15

申请号：PCT/KR2008/004102

申请日：2008-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： PI, Zhouyue ,  KHAN, Farooq

IPC: H03M13/09 ,  H03M13/00

CPC classification number: H04L1/004 ,  H03M13/09 ,  H03M13/091 ,  H03M13/2906 ,  H03M13/2966 ,  H03M13/6306 ,  H03M13/6525 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0075

Abstract: A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. A transport block CRC is calculated for a transport block including a plurality of information bit. A transport block including the transport block CRC is segmented into a plurality of subsets and a plurality of cyclic redundancy checks are calculated for the plurality of subsets. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.

Abstract translation: 一种用于产生循环冗余校验的方法和电路。 该方法对具有多个信息比特的传输块计算多个循环冗余校验。 对包括多个信息比特的传输块计算传输块CRC。 包括传输块CRC的传输块被分割成多个子集，并且为多个子集计算多个循环冗余校验。 基于信息比特的子集来计算多个循环冗余校验中的至少一个循环冗余校验。 此外，可以基于所有信息比特来计算传输块循环冗余校验。

公开(公告)号：WO2007143277A2

公开(公告)日：2007-12-13

申请号：PCT/US2007/066522

申请日：2007-04-12

Applicant: AWARE, INC. ,  TZANNES, Marcos, C.

Inventor： TZANNES, Marcos, C.

IPC: H04L12/56

CPC classification number: H04L45/72 ,  H03M13/00 ,  H03M13/09 ,  H03M13/091 ,  H03M13/2707 ,  H03M13/6513 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/08 ,  H04L1/1607 ,  H04L1/18 ,  H04L1/1809 ,  H04L1/1835 ,  H04L1/1874 ,  H04L12/5601 ,  H04L45/00 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/32 ,  H04L49/552 ,  H04L69/324 ,  H04L2012/5647

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Abstract translation: 通过识别不同的分组类型，可以基于分配的分组处理标识符来处理分组。 例如，该标识符可以不延迟地转发等待时间敏感的分组，并且允许存储用于可能重传的错误敏感分组。 在另一实施例中，并且可选地与包括分组处理标识符的重传协议相结合，用于分组重传的存储器可以与诸如编码，解码，交织，去交织，纠错等的其他收发器功能共享。

公开(公告)号：WO0176077A3

公开(公告)日：2002-04-04

申请号：PCT/CA0100410

申请日：2001-03-30

Applicant: SZYMANSKI TED

Inventor： SZYMANSKI TED

IPC: H03M13/09 ,  H03M13/15 ,  H04L1/00 ,  H04L1/18 ,  H04B10/155

CPC classification number: H04L1/0057 ,  H03M13/09 ,  H03M13/091 ,  H03M13/15 ,  H03M13/6575 ,  H04L1/0043 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/1809 ,  H04L1/1816 ,  H04L1/1835 ,  H04L1/1874

Abstract: Transmitters, receivers, and coding schemes to increase data rate and decrease bit error rate of an optical data link are disclosed. Data is transmitted across the link with a less than nominal bit error rate (BER), by encoding the data using a forward error correction (FEC) code or by requesting retransmission of transmitted packets in error. Data is transmitted at a speed that introduces errors at a rate that is in excess of the nominal BER but that may be corrected using the FEC code or retransmission so that the data may be received with less than the nominal BER. The data rate is increased as the link operating speed is increased beyond the overhead required by the FEC codes or retransmission. High speed FEC encoders and decoders facilitating such transmission are disclosed.

Abstract translation: 公开了用于增加数据速率并降低光数据链路的误码率的发射机，接收机和编码方案。 通过使用前向纠错（FEC）码对数据进行编码或者通过请求错误发送的数据包的重传，通过小于标称误码率（BER）的链路传输数据。 数据以以超过标称BER的速率引入误差的速度发送，但是可以使用FEC码或重传来校正数据，以便可以以小于标称BER的速率接收数据。 数据速率随着链路运行速度增加而超过FEC码或重传所需的开销而增加。 公开了促进这种传输的高速FEC编码器和解码器。

公开(公告)号：WO0161868A3

公开(公告)日：2002-02-21

申请号：PCT/US0105477

申请日：2001-02-20

Applicant: ANALOG DEVICES INC

Inventor： RIFAAT RASEKH ,  LERNER BORIS

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/11 ,  H04L1/00

CPC classification number: H03M13/091 ,  H03M13/6569

Abstract: A method, apparatus and product for user in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder based code for the specified data, in response to the plurality of preliminary remainder based codes. In one embodiment, the plurality of preliminary remainder based codes includes at least two preliminary remainder based codes each generated in response to a respective portion of the specified data. In another embodiment, at least two preliminary remained based codes are generated at least partially concurrently with one another.

Abstract translation: 用于生成基于余数的代码的用户的方法，装置和产品响应于指定的数据生成多个基于初步余数的代码，并且响应于多个初步的基于余数的代码来合成用于指定数据的基于余数的代码。 在一个实施例中，多个初步的基于余数的码包括至少两个基于剩余的基于码的代码，每个代码响应于指定数据的相应部分而产生。 在另一个实施例中，至少部分地同时地产生至少两个基于暂留的基于代码的代码。

公开(公告)号：WO00025432A1

公开(公告)日：2000-05-04

申请号：PCT/SE1999/001842

申请日：1999-10-13

IPC: H03M20060101 ,  H03M13/00

CPC classification number: H03M13/091

Abstract: The present invention relates to a receiving arrangement receiving digitally coded data signals transported over a channel. The data signal comprises sequences divided into blocks and the receiving arrangement includes error correcting means providing a number of alternative blocks. Further it comprises error detecting means and storing means for storing information relating to each possible block position of a sequence. The error detecting means comprises a differential CRC-decoder including first decoding means (20A) for decoding a sequence of blocks using a reference sequence to provide a reference syndrome, and second decoding means (20B) for decoding selected alternative differential blocks of the sequence obtainable via the error correcting means. The differential blocks are calculated as a difference between the corresponding block of the reference sequence and alternative blocks respectively to provide differential syndroms. The resulting syndroms are calculated as a sum of the reference syndrome and of a number of differential syndromes respectively. The invention also relates to a system including such receiving arrangement, an error correcting CRC-decoder and a method of detecting errors in a CRC-coded digital signal.

Abstract translation: 本发明涉及一种接收通过信道传输的数字编码数据信号的接收装置。 数据信号包括分成块的序列，并且接收装置包括提供多个备选块的纠错装置。 此外，它包括误差检测装置和用于存储与序列的每个可能的块位置有关的信息的存储装置。 误差检测装置包括差分CRC解码器，其包括用于使用参考序列解码块序列以提供参考校正子的第一解码装置（20A），以及用于对可获得的序列的所选替代差分块进行解码的第二解码装置（20B） 经由纠错装置。 差分块被分别计算为参考序列和替代块的相应块之间的差异以提供差异综合征。 所得到的综合征分别计算为参考综合征和多个差异综合征的总和。 本发明还涉及一种包括这种接收装置，纠错CRC解码器和检测CRC编码数字信号中的错误的方法的系统。

公开(公告)号：WO1995012921A1

公开(公告)日：1995-05-11

申请号：PCT/US1994012138

申请日：1994-10-18

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: H03M13/00

CPC classification number: H03M13/091 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1068 ,  G11B20/1833 ,  H03M13/09 ,  H03M13/35

Abstract: One-stage and two-stage CRC generation systems (400, 600) feature a CRC generator/checker (700) comprising a segmenter (710) of an input data stream into substreams, a circuit (712) forming a linear combination of the substreams and generating CRC bytes therefrom, and a checker (714) comparing the CRC bytes with previously generated CRC bytes. The two-stage system (600) includes a first CRC generator/checker (601) generating primary CRC bytes, a memory (602) receiving the input data and the primary CRC bytes, and a second CRC generator/checker (603) generating verification CRC bytes for comparison with the primary CRC bytes to check the input data after retrieval from the memory (602) and before input to an encoder (604). The second CRC generator/checker (603) can optionally apply some of the verification CRC bytes to the encoder (604) for use as secondary CRC bytes. The number of CRC bytes outputted by the CRC generator/checkers (601, 603) is programmable.

Abstract translation: 一级和两级CRC生成系统（400,600）具有CRC生成器/检查器（700），其包括输入数据流的分段器（710），进入子流，电路（712）形成子流的线性组合 以及从其生成CRC字节;以及检查器（714），将CRC字节与先前产生的CRC字节进行比较。 两级系统（600）包括：生成主CRC字节的第一CRC生成器/检查器（601），接收输入数据和主CRC字节的存储器（602）;以及生成验证的第二CRC生​​成器/检查器（603） CRC字节用于与主CRC字节进行比较，以在从存储器（602）检索并在输入到编码器（604）之前检查输入数据。 第二CRC生​​成器/检查器（603）可以可选地将一些验证CRC字节应用于编码器（604）以用作次级CRC字节。 由CRC发生器/检查器（601,603）输出的CRC字节的数量是可编程的。

公开(公告)号：WO1994015407A1

公开(公告)日：1994-07-07

申请号：PCT/US1993011790

申请日：1993-12-06

Applicant: CODEX CORPORATION

Inventor： CODEX CORPORATION ,  LI, Shiping ,  PASCO-ANDERSON, James, A.

IPC: H03M13/00

CPC classification number: H03M13/091

Abstract: Various parallel CRC remainder coefficient generation devices (100, 200, 300, 400, 500, 600, 700) and methods (1100, 1200) are described for providing efficient error detection in various digital data communication systems (800, 900, 1000). A K-bit CRC remainder is calculated from m bits at a time, where m can be less than, equal to, or greater than K, and where the processing of each of the m bits requires a total of j K-bit table look-ups into a total of j tables (410, 412, 414, 516, 518, 520, 522, 616, 614, 712, 714) of 2 entries each, where m = jb. Also required are one m-bit exclusive-or operation (208, 306, 506, 608, 706), a total of (j-1)K-bit exclusive-or operations (422, 532, 626, 628, 720), and one (K-m)-bit exclusive-or operation (216, 632) if m

Abstract translation: 描述了用于在各种数字数据通信系统（800,900,1000）中提供有效的错误检测的各种并行CRC余数系数产生装置（100,200,300,400,500,600,700）和方法（1100,1200）。 一个K位CRC余数由m位计算，其中m可以小于，等于或大于K，并且每个m位的处理需要总共j个K位表 - 分别组合成每个2个条目的总共j个表（410,412,414,516,518,520,522,616,614,712,714），其中m = jb。 还需要一个m位异或操作（208,306,506,608,706），总共（j-1）个K位异或运算（422,532,626,628,720）， 如果m