公开(公告)号：WO2020139761A1

公开(公告)日：2020-07-02

申请号：PCT/US2019/067866

申请日：2019-12-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： PULUGURTHA, Srinivas ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L27/108

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. The first data line is electrically coupled to a first channel region of a first transistor. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to a second channel region of a second transistor, the second channel region electrically coupled to the charge storage structure and being between a charge storage structure of the first transistor and the third data line. The first access line is located on a first level of the apparatus. The second access line is located on a second level of the apparatus. The charge storage structure is located on a level of the apparatus between the first and second levels.

公开(公告)号：WO2020139710A1

公开(公告)日：2020-07-02

申请号：PCT/US2019/067554

申请日：2019-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  PULUGURTHA, Srinivas ,  LIU, Haitao ,  SARPATWARI, Karthik ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L27/108

Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

公开(公告)号：WO2020076766A1

公开(公告)日：2020-04-16

申请号：PCT/US2019/055113

申请日：2019-10-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： RAMASWAMY, Durai Vishak Nirmal

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/02

Abstract: A method of forming a device comprises forming sacrificial pillar structures over conductive structures overlying a barrier structure substantially impermeable to hydrogen. The sacrificial pillar structures are separated from one another by trenches linearly extending in a first lateral direction orthogonal to a second lateral direction in which the conductive structures linearly extend. Gate electrodes are formed within the trenches and laterally adjacent sidewalls of the sacrificial pillar structures. The sacrificial pillar structures are removed to form openings between the gate electrodes. Dielectric liner structures are formed within the openings and laterally adjacent sidewalls of the gate electrodes. Channel structures are formed within the openings after forming the dielectric liner structures. The channel structures comprise a semiconductive material having a band gap larger than that of polycrystalline silicon. Conductive contacts are formed on the channel structures. A device, a memory device, and an electronic system are also described.

公开(公告)号：WO2020076652A1

公开(公告)日：2020-04-16

申请号：PCT/US2019/054838

申请日：2019-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  PRALL, Kirk D. ,  LIU, Haitao ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L29/786

Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.

公开(公告)号：WO2019046629A1

公开(公告)日：2019-03-07

申请号：PCT/US2018/048934

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  LIU, Haitao ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L29/786 ,  H01L27/105

Abstract: A semiconductor device is disclosed. The semiconductor device includes a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material. Memory arrays, semiconductor devices, and systems incorporating memory cells, and hybrid transistors are also disclosed, as well as related methods for forming and operating such devices.

公开(公告)号：WO2017222786A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/035758

申请日：2017-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CALDERONI, Alessandro ,  RAMASWAMY, Durai Vishak Nirmal ,  PRALL, Kirk ,  BEDESCHI, Ferdinando

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described, A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

Abstract translation: 描述了用于操作一个或多个铁电存储器单元的方法，系统和设备。单元可以被写入具有旨在传达与典型地与该值相关联的不同逻辑状态的值的值 。 例如，已经存储与一个逻辑状态相关的电荷一段时间的单元可以被重新写入以存储不同的电荷，并且重写的单​​元仍可以被读取以具有原始存储的逻辑状态。 指示器可被存储在锁存器中以指示当前由单元存储的逻辑状态是否是单元的预期逻辑状态。 例如，可以基于事件的发生或者基于确定小区已经存储了一个值（或电荷）达特定时间段，来周期性地重新写入小区。

公开(公告)号：WO2016133611A1

公开(公告)日：2016-08-25

申请号：PCT/US2016/013174

申请日：2016-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  TAO, Qian ,  RAMASWAMY, Durai Vishak Nirmal ,  LIU, Haitao ,  PRALL, Kirk D. ,  CHAVAN, Ashonita A.

IPC: G11C11/22

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit- parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Abstract translation: 存储单元包括与选择装置串联电耦合的选择装置和电容器。 该电容器包括两个导电电容器电极，其间具有铁电材料。 该电容器具有从电容器电极中的一个通过铁电材料到另一个的本征电流泄漏路径。 存在从一个电容器电极到另一个电容器电极的平行电流泄漏路径。 并联电流泄漏路径与固有路径电路平行，总内阻小于固有路径。 公开其他方面。

公开(公告)号：WO2023076261A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/047720

申请日：2022-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  FACKENTHAL, Richard E. ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H10B12/00 ,  G11C11/4097 ,  G11C8/14 ,  H01L29/788

Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.

公开(公告)号：WO2022182838A1

公开(公告)日：2022-09-01

申请号：PCT/US2022/017653

申请日：2022-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  LIU, Haitao ,  SARPATWARI, Karthik ,  RAMASWAMY, Durai Vishak Nirmal ,  CALDERONI, Alessandro ,  FACKENTHAL, Richard E. ,  MILLS, Duane R.

IPC: H01L27/108 ,  H01L29/78

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

公开(公告)号：WO2021041567A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/048033

申请日：2020-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  SARPATWARI, Karthik ,  LIU, Haitao ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L27/108 ,  H01L27/02 ,  G11C11/402

Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.