公开(公告)号：WO1998025271A1

公开(公告)日：1998-06-11

申请号：PCT/JP1996003548

申请日：1996-12-04

Applicant: HITACHI, LTD. ,  NOGUCHI, Koki ,  MICHISHITA, Satoshi ,  HORIGUCHI, Masashi ,  KUBO, Masaharu ,  MIYAMOTO, Toshio ,  NISHIMURA, Asao

Inventor： HITACHI, LTD.

IPC: G11C11/407

CPC classification number: G11C11/409 ,  G11C11/406

Abstract: A semiconductor integrated circuit device for high-speed data transfer, wherein wait control is eliminated to allow a logic circuit to access a DRAM during the self-refreshing period of the DRAM. The integrated circuit comprises a chip that includes a microcomputer incorporated with a CPU, memories and peripheral circuits, and a flash memory; and another chip that includes DRAMs and a logic circuit, such as an ASIC. The control of the DRAM depends on whether the DRAM is in the normal access period or in the self-refreshing period. In the DRAM self-refreshing period, the refreshing operations are canceled so that the logic circuit can access the DRAM when the logic circuit requests the access to the DRAM by using readout/write signals R/W.

Abstract translation: 一种用于高速数据传输的半导体集成电路装置，其中消除了等待控制，以允许逻辑电路在DRAM的自刷新周期期间存取DRAM。 集成电路包括芯片，其包括与CPU结合的微计算机，存储器和外围电路以及闪速存储器; 以及包括DRAM和诸如ASIC的逻辑电路的另一芯片。 DRAM的控制取决于DRAM是处于正常访问周期还是在自刷新期间。 在DRAM自刷新周期中，刷新操作被取消，使得当逻辑电路通过使用读出/写入信号R / W请求访问DRAM时逻辑电路可以访问DRAM。

公开(公告)号：WO1998024939A1

公开(公告)日：1998-06-11

申请号：PCT/JP1996003585

申请日：1996-12-06

Applicant: HITACHI, LTD. ,  SATOU, Kazuhiko ,  SATOU, Kouji ,  YASUDA, Takeshi ,  YAMADA, Ryokichi ,  ARATO, Toshiaki ,  KANEKO, Tomoko ,  YAMASHITA, Hisao ,  AZUHATA, Shigeru ,  HASEGAWA, Tsutomu

Inventor： HITACHI, LTD.

IPC: C22B07/00

CPC classification number: C22B25/06 ,  C22B7/004 ,  Y02P10/228

Abstract: A method and an apparatus for separating and recovering solder from a device or component, such as a printed board mounted with electronic parts. A heat medium made of solid particles or a liquid is used. This heat medium is brought into contact with a device or component so as to melt the solder with the heat transmitted from the heat medium thereto and apply an impact force to a soldered portion by means of the heat medium. A portion soldered has a high wettability with solder, and the solder cannot be separated therefrom by merely melting the same. However, the method enables the solder to be separated at a separation rate of as high as over 95 %.

Abstract translation: 一种用于从装置或组件（例如安装有电子部件的印刷电路板）分离和回收焊料的方法和装置。 使用由固体颗粒或液体制成的热介质。 该热介质与装置或部件接触，以便利用从热介质传递的热量来熔化焊料，并通过热介质将冲击力施加到焊接部分。 焊接的部分与焊料具有高的润湿性，并且通过仅使其熔化，焊料不能与其分离。 然而，该方法能够以高达95％以上的分离速率分离焊料。

公开(公告)号：WO1998024027A1

公开(公告)日：1998-06-04

申请号：PCT/JP1996003448

申请日：1996-11-25

Applicant: HITACHI, LTD. ,  YAMAMOTO, Kazumichi ,  UMETANI, Yukio ,  SUZUKI, Norihiro ,  YAMAGUCHI, Muneaki

Inventor： HITACHI, LTD.

IPC: G06F12/00

CPC classification number: G06F17/30902

Abstract: A cache structure of a World Wide Web (WWW) client apparatus for improving utilization efficiency and reducing access time to information. A cache is constituted in an HDD or DVD-RAM by the control of a Web cache program and a copy of retrieved information is stored in it. A directory of the cache is managed by a Web cache management table, and control is made so that the entries necessary for the cache contents and the management table are stored before the DVD-RAM is removed from the apparatus. The client operation can be smoothly continued by loading the DVD-RAM to another client apparatus, or if an information provider stores the information in the Web cache from and provides it, the information can be browsed by the same URL as the WWW access.

Abstract translation: 万维网（WWW）客户端设备的缓存结构，用于提高利用效率并减少访问信息的时间。 通过控制Web缓存程序在HDD或DVD-RAM中构成缓存，并且存储检索到的信息的副本。 高速缓存的目录由Web缓存管理表进行管理，并且进行控制，使得在从设备移除DVD-RAM之前，高速缓存内容和管理表所需的条目被存储。 可以通过将DVD-RAM加载到另一个客户端设备来平滑地继续客户端操作，或者如果信息提供者将信息存储在Web缓存中并提供给它，则可以通过与WWW访问相同的URL浏览该信息。

公开(公告)号：WO1998021691A1

公开(公告)日：1998-05-22

申请号：PCT/JP1997004123

申请日：1997-11-12

Applicant: HITACHI, LTD. ,  ISHIFUJI, Tomoaki ,  NISHINO, Toshikazu ,  SAITOH, Takeshi ,  SHIDA, Masaaki

Inventor： HITACHI, LTD.

IPC: G06K17/00

CPC classification number: G06K7/10059 ,  G06K7/0008

Abstract: A method for accurately identifying identification codes of a plurality of non-contact IC cards. On receiving transmission of an interrogation signal (801) from an identification apparatus, an IC card transmits a predetermined number of bits of identification code. The identification apparatus receives the predetermined number of bits transmitted thereto (803), and returns the predetermined number of bits to the IC card (804). The IC card in which the returned bits are equal to the bits transmitted from this IC card transmits a predetermined number of bits following the bits of the previous transmission, and similar processing is repeated. Thus, even when the number of IC cards which simultaneously transmit identification codes is increased, reduction in identification efficiency is prevented.

Abstract translation: 一种用于准确识别多个非接触式IC卡的识别码的方法。 在从识别装置接收到询问信号（801）的传输时，IC卡发送预定数量的识别码位。 识别装置接收发送到其的预定位数（803），并将预定位数返回给IC卡（804）。 其中返回的位等于从该IC卡发送的位的IC卡发送先前传输的比特之后的预定数量的比特，并且重复类似的处理。 因此，即使当同时发送识别码的IC卡的数量增加时，也可以防止识别效率的降低。

公开(公告)号：WO1998020564A1

公开(公告)日：1998-05-14

申请号：PCT/JP1997003964

申请日：1997-10-30

Applicant: HITACHI, LTD. ,  HITACHI MICROCOMPUTER SYSTEM, LTD. ,  ISHIZUKA, Hiroyasu ,  OKUYAMA, Kousuke ,  KUBOTA, Katsuhiko

Inventor： HITACHI, LTD. ,  HITACHI MICROCOMPUTER SYSTEM, LTD.

IPC: H01L29/87

CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device which is provided with a protective element of a thyristor structure for protecting an internal circuit from positive overvoltage, and a protective element consisting of a diode (D1) for protecting the internal circuit from negative overvoltage, between an external terminal (2) and earth potential (GND) so as to remove the difference in ESD resistance caused by the polarity of overvoltage applied to the external terminal and improve the ESD resistance to both positive and negative overvoltage of the device.

Abstract translation: 一种半导体集成电路器件，其具有用于保护内部电路免于正过电压的晶闸管结构的保护元件，以及由内部电路保护内部电路不受负过电压的二极管（D1）组成的保护元件，外部端子 2）和接地电位（GND），以消除由施加到外部端子的过电压极性引起的ESD电阻差异，并提高器件的正负过压的ESD电阻。

公开(公告)号：WO1998019242A1

公开(公告)日：1998-05-07

申请号：PCT/JP1996003172

申请日：1996-10-30

Applicant: HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORP. ,  YAMAZAKI, Takanaga ,  AKAO, Yasushi ,  KURAKAZU, Keiichi ,  OHIZUMI, Masayasu ,  KATAOKA, Takeshi ,  NAKAI, Tatsuo ,  MIYAZAKI, Mitsuhiro ,  MURAYAMA, Yosuke

Inventor： HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORP.

IPC: G06F12/08

CPC classification number: G06F12/0864

Abstract: A data processor including a central processing unit, a plurality of direct map cache memories (3, 4), and a plurality of area designation circuits (5, 6) for designating variably the positions and the sizes of address areas in a memory space managed by the central processing unit, wherein the address areas designated by a plurality of area designation circuits are partially overlapped, so that the overlapped area (Eco) functions as two-way set associative cache memories by combining a plurality of cache memories. Each cache memory functions as a direct map cache memory for the non-overlap area. Information is predetermined about locations of routines in the address area and the required speed for desirable data processing. When a cache object area is assigned to a plurality of cache memories, they are operated as a set associative cache for a task or a data area particularly requiring a higher operation speed. In this way, the cache hit rate in a necessary area can be improved and the system can be optimized.

Abstract translation: 一种数据处理器，包括中央处理单元，多个直接地图高速缓冲存储器（3,4）和多个区域指定电路（5,6），用于可变地指定管理的存储器空间中的地址区域的位置和大小 通过中央处理单元，其中由多个区域指定电路指定的地址区域部分重叠，从而通过组合多个高速缓冲存储器，重叠区域（Eco）用作双向组关联高速缓存存储器。 每个缓存存储器用作非重叠区域的直接映射缓存存储器。 关于地址区域中的例程的位置和期望的数据处理所需的速度预先确定信息。 当将高速缓存对象区域分配给多个高速缓存存储器时，它们被操作为特定需要较高操作速度的任务或数据区域的组合关联高速缓存。 以这种方式，可以提高必要区域中的高速缓存命中率，并且可以优化系统。

公开(公告)号：WO1998018009A1

公开(公告)日：1998-04-30

申请号：PCT/JP1996003084

申请日：1996-10-23

Applicant: HITACHI, LTD. ,  KURIYAMA, Hiroyuki ,  KATAYAMA, Atsushi ,  MITSUMAKI, Hiroshi ,  HOHMANN, Peter

Inventor： HITACHI, LTD.

IPC: G01N35/04

CPC classification number: G01N35/04 ,  G01N35/025 ,  G01N35/026 ,  G01N2035/00306 ,  G01N2035/00326 ,  Y10T436/112499 ,  Y10T436/113332 ,  Y10T436/114165

Abstract: A biochemical analyzer for automatically analyzing components of a sample, including a sample rack conveyor portion, a sample charging portion, an analyzer portion and a sample accommodation portion that are independtly constituted, wherein the sample charging portion, the analyzer portion and the sample accommodation portion are interconnected and are disposed in the longitudinal direction of the sample rack conveyor portion. The sample charging portion, the analyzer portion and the sample accommodation portion are standardized to a size having a height of 850 mm to 950 mm above the floor of the installation space and a depth of 750 mm to 800 mm, and their transverse width is equal to a multiple of the length of the sample rack. Further, an identification portion representing that it is the analyzing portion is disposed on the front surface side of the analyzer portion. Since the outer size of each portion is standardized and has well balanced feeling of unity, and since the height of an inspection chamber is unified at a low position, the entire portion of the inspection chamber can be looked over and gives a light and broad feeling. Therefore, it can control senses of people and can provide a plaesant inspection environment to an inspection engineer.

Abstract translation: 一种用于自动分析样品的组分的生物化学分析装置，包括样品架输送机部分，样品充电部分，分析器部分和样品容纳部分，其独立地构成，其中样品充电部分，分析器部分和样品容纳部分 相互连接并沿样品架传送部分的纵向设置。 样本充电部分，分析器部分和样本容纳部分被标准化为在安装空间的地板上方高度为850mm至950mm的高度，并且深度为750mm至800mm，并且它们的横向宽度相等 到样品架的长度的倍数。 此外，表示分析部分的识别部分设置在分析器部分的前表面侧。 由于每个部分的外部尺寸是标准化的并且具有良好的平衡感觉，并且由于检查室的高度在低位置处于一体，所以可以看到整个检查室的整个部分并且产生光和广泛的感觉 。 因此，它可以控制人的感觉，并可以向检验工程师提供一个检查环境。

公开(公告)号：WO1998017617A1

公开(公告)日：1998-04-30

申请号：PCT/JP1997003190

申请日：1997-09-10

Applicant: HITACHI, LTD. ,  SASAKI, Hiroshi ,  SHOUJI, Mitsuyoshi ,  NAKAKAWAJI, Takayuki ,  TAKAMURA, Tomoe ,  ISHIDA, Mina ,  ITOU, Yutaka ,  MATSUMOTO, Hiroyuki

Inventor： HITACHI, LTD.

IPC: C07C43/12

CPC classification number: G11B5/7315 ,  C07C233/25 ,  C08G65/007 ,  C09D171/02 ,  C09K3/18 ,  C10M105/54 ,  C10M105/68 ,  C10M105/70 ,  C10M107/38 ,  C10M107/40 ,  C10M2211/042 ,  C10M2211/044 ,  C10M2211/06 ,  C10M2215/08 ,  C10M2215/082 ,  C10M2215/22 ,  C10M2215/221 ,  C10M2215/225 ,  C10M2215/226 ,  C10M2215/28 ,  C10M2215/30 ,  C10N2240/20 ,  C10N2240/201 ,  C10N2240/202 ,  C10N2240/203 ,  C10N2240/204 ,  C10N2240/205 ,  G11B5/71 ,  G11B5/725

Abstract: The use of a fluorocompound comprising a perfluoropolyoxyalkyl/alkylene chain with an average molecular weight of not less than 800 and an atomic group of a cyclic/noncyclic polyether as a low-scattering lubricant/surface modifier (such as a water repellant) serves to improve the sliding durability of magnetic recording media.

Abstract translation: 使用包含平均分子量不低于800的全氟聚氧烷基/亚烷基链和作为低散射润滑剂/表面改性剂（例如防水剂）的环状/非环状聚醚的原子团的氟化合物用于改善 磁记录介质的滑动耐久性。

公开(公告)号：WO1998015899A1

公开(公告)日：1998-04-16

申请号：PCT/JP1996002908

申请日：1996-10-07

Applicant: HITACHI, LTD. ,  MATSUDA, Koji ,  MIYAZAKI, Yoshihiro ,  TAKAYA, Soichi

Inventor： HITACHI, LTD.

IPC: G06F15/16

CPC classification number: G06F11/16

Abstract: A clock-synchronized fault-tolerant computer system comprising a plurality of processors, a plurality of main memory devices, a plurality of I/O devices, buses connecting them, a separation/coupling unit for separating/coupling at least one processor, at least one main memory device and at least one I/O device as one computer system, an instruction unit for giving a separation/coupling instruction to the separation/coupling unit, and a status memory for storing at least two states, that is, the same operation and an independent operation. At least one processor, at least one memory device and at least one I/O device are combined to form one independent computer system, in which a software replacement is executed. This computer system is then operated in synchronism with other computer systems, thus permitting software to be replaced without stopping the system.

Abstract translation: 一种时钟同步的容错计算机系统，包括多个处理器，多个主存储器装置，多个I / O装置，连接它们的总线，用于分离/耦合至少一个处理器的分离/耦合单元，至少 一个主存储器装置和至少一个作为一个计算机系统的I / O装置，用于向分离/耦合单元提供分离/耦合指令的指令单元以及用于存储至少两个状态的状态存储器，即相同 操作和独立操作。 至少一个处理器，至少一个存储器设备和至少一个I / O设备被组合以形成其中执行软件替换的一个独立的计算机系统。 然后，该计算机系统与其他计算机系统同步操作，从而允许在不停止系统的情况下更换软件。

公开(公告)号：WO1998015668A1

公开(公告)日：1998-04-16

申请号：PCT/JP1996002907

申请日：1996-10-07

Applicant: HITACHI, LTD. ,  HIDAKA, Kishio ,  ARIKAWA, Hideyuki ,  OHASHI, Tetuya ,  KOJIMA, Yoshitaka ,  NAKAMURA, Shigeyoshi

Inventor： HITACHI, LTD.

IPC: C23C14/48

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  C23C14/0031 ,  G11B5/3967 ,  G11B2005/3996

Abstract: A method for producing a low-cost laminate comprising a functional thin film. More concretely, a substrate is irradiated with an ion beam in an atmosphere containing different kinds of vaporized materials so as to deposit different materials one on another.

Abstract translation: 一种制造包含功能性薄膜的低成本层压体的方法。 更具体地，在含有不同种类的汽化材料的气氛中用离子束照射基板，以便将不同的材料彼此沉积。