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    METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
    2.
    发明申请
    METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM 审中-公开
    用于在记忆系统中校准写入时序的方法和装置

    公开(公告)号：WO2009082502A1

    公开(公告)日：2009-07-02

    申请号：PCT/US2008/055661

    申请日：2008-03-03

    申请人： RAMBUS INC. ,  GIOVANNINI, Thomas ,  GUPTA, Alok ,  SHAEFFER, Ian ,  WOO, Steven C.

    发明人： GIOVANNINI, Thomas ,  GUPTA, Alok ,  SHAEFFER, Ian ,  WOO, Steven C.

    IPC分类号： G11C7/22 ,  G11C11/40

    CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

    摘要： A memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. The phase detector on the memory chip receives signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. The phase detector uses the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

    摘要翻译： 存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变数据选通确认操作的延迟， 选通相对于时钟信号的时钟周期的倍数。 存储器芯片上的相位检测器从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记时钟信号中的特定时钟周期的脉冲。 相位检测器使用标记信号来画定时钟信号中的特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生反馈信号，该信号被返回到存储器控制器以便于校准 时间关系。

    A METHOD OF SYNCHRONIZING READ TIMING IN A HIGH SPEED MEMORY SYSTEM
    3.
    发明申请
    A METHOD OF SYNCHRONIZING READ TIMING IN A HIGH SPEED MEMORY SYSTEM 审中-公开
    一种同步高速存储器系统中的读时序的方法

    公开(公告)号：WO02069341A3

    公开(公告)日：2002-11-28

    申请号：PCT/US0202764

    申请日：2002-02-01

    申请人： MICRON TECHNOLOGY INC

    发明人： JANZEN JEFFERY W ,  MANNING TROY A ,  MARTIN CHRIS G ,  KEETH BRENT

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409

    CPC分类号： G11C7/1066 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C2207/107 ,  G11C2207/2254 ,  G11C2207/2281

    摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

    摘要翻译： 通过使用至少一个标志信号来均衡高速同步存储器子系统中的多个存储器装置的读取等待时间。 标记信号具有等同的信号传播特性读取时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储装置将开始以预定数量的时钟周期输出与先前接收的读取命令相关联的数据。 对于标志信号中的每一个，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取等待时间之间所需的延迟。 然后在存储器系统的正常操作期间将延迟应用于读取事务。

    METHOD OF OPERATING AN SRAM MOS TRANSISTOR STORAGE CELL
    4.
    发明申请
    METHOD OF OPERATING AN SRAM MOS TRANSISTOR STORAGE CELL 审中-公开
    一种用于操作SRAM MOS晶体管存储单元

    公开(公告)号：WO1997023878A2

    公开(公告)日：1997-07-03

    申请号：PCT/DE1996002394

    申请日：1996-12-12

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  BERTHOLD, Jörg ,  DRESEL, Jürgen

    发明人： SIEMENS AKTIENGESELLSCHAFT

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419 ,  G11C11/409

    摘要： The 6-transistor storage cell consists of two regenerative inverters (MN5, MP3; MN6, MP4) connected via a selector transistor (MN1, MN2) controlled by a word line (WL, WLS) to a bit line (BL, BLQ). When data are entered in the storage cell, both selector transistors are conductively driven. Only the first selector transistor (MN1) is conductively driven on the read-out of the content of the cell, while the other remains blocked. Thus, on read-out, only one bit line (BL) is reverse-charged.

    摘要翻译： 的存储单元由包含两个反向耦合的反相器（MN5，MP3; MN6，MP4）的6晶体管存储器单元，通过连接的字线的（WL，WLS）选择晶体管（MN1，MN2）与位线（BL，BLQ）之一分别驱动 是。 当将信息写入到所述存储单元都选择晶体管导通。 当读出该单元中的内容，仅在第一选择晶体管（MN1）导通，另一选择晶体管（MN2）保持阻塞。 以这种方式，仅读取位线（BL）被传送。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：WO2011086846A1

    公开(公告)日：2011-07-21

    申请号：PCT/JP2010/073642

    申请日：2010-12-20

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  KATO, Kiyoshi

    发明人： YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  KATO, Kiyoshi

    IPC分类号： H01L21/8247 ,  G11C11/402 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C11/409 ,  G11C11/404 ,  G11C16/02

    摘要： An object is to provide a semiconductor device in which stored data can be retained even when power is not supplied, and there is no limitation on the number of write cycles. The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, a memory cell connected between the source line and the bit line, a first driver circuit electrically connected to the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line and the source line. The first transistor is formed using a semiconductor material other than an oxide semiconductor. The second transistor is formed using an oxide semiconductor material.

    摘要翻译： 目的在于提供一种半导体器件，其中即使在未提供电源的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体器件包括源极线，位线，第一信号线，第二信号线，字线，连接在源极线和位线之间的存储单元，电连接到位线的第一驱动器电路， 电连接到第一信号线的第二驱动电路，与第二信号线电连接的第三驱动电路，和电连接到字线和源极线的第四驱动电路。 第一晶体管使用除氧化物半导体之外的半导体材料形成。 第二晶体管使用氧化物半导体材料形成。

    METHOD AND APPARATUS FOR SHARING SENSE AMPLIFIERS BETWEEN MEMORY BANKS
    8.
    发明申请
    METHOD AND APPARATUS FOR SHARING SENSE AMPLIFIERS BETWEEN MEMORY BANKS 审中-公开
    用于在存储器之间共享感知放大器的方法和装置

    公开(公告)号：WO1998029874A1

    公开(公告)日：1998-07-09

    申请号：PCT/US1997023106

    申请日：1997-12-17

    申请人： RAMBUS, INC.

    发明人： RAMBUS, INC. ,  BARTH, Richard, M. ,  STARK, Donald, C. ,  TSERN, Ely, K.

    IPC分类号： G11C07/00

    CPC分类号： G11C7/06 ,  G11C7/00 ,  G11C11/409

    摘要： A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to both the first memory bank and the second memory bank. The multiple sense amplifiers are configured for use by both the first memory bank and the second memory bank, but not simultaneously. A control mechanism is used to avoid accessing the first memory bank and the second memory bank simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks.

    摘要翻译： 存储器件包括第一存储体和第二存储体，每个存储体具有至少一个存储单元的子阵列。 多感测放大器耦合到第一存储体和第二存储体两者。 多个读出放大器被配置为由第一存储器组和第二存储器组使用，但不能同时使用。 使用控制机制来避免同时访问第一存储体和第二存储体。 存储器组之间的读出放大器的共享使由附加存储体引起的管芯面积损失最小化。

    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS
    9.
    发明申请
    COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS 审中-公开
    使用存储器设备生成的参考信号协调存储器操作

    公开(公告)号：WO2011106055A4

    公开(公告)日：2011-11-03

    申请号：PCT/US2010058542

    申请日：2010-12-01

    申请人： RAMBUS INC ,  BEST SCOTT C ,  SHAEFFER IAN

    发明人： BEST SCOTT C ,  SHAEFFER IAN

    IPC分类号： G06F13/16 ,  G06F13/38

    CPC分类号： G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02B60/1228 ,  Y02D10/14

    摘要： A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

    摘要翻译： 存储器系统包括耦合到多个存储器设备的存储器控​​制器。 每个存储器设备包括振荡器，该振荡器生成内部参考信号，该内部参考信号以作为存储器设备内的物理设备结构的函数的频率振荡。 内部参考信号的频率因此是设备特定的。 每个存储器设备从其内部参考信号产生共享参考信号并将共享参考信号传送到公共存储器控制器。 存储器控制器使用共享参考信号从每个存储器设备恢复设备特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器设备通信。

    SRAM YIELD ENHANCEMENT BY READ MARGIN IMPROVEMENT
    10.
    发明申请
    SRAM YIELD ENHANCEMENT BY READ MARGIN IMPROVEMENT 审中-公开
    通过阅读改进的SRAM YIELD增强

    公开(公告)号：WO2010021979A1

    公开(公告)日：2010-02-25

    申请号：PCT/US2009/054028

    申请日：2009-08-17

    申请人： QUALCOMM INCORPORATED ,  CHEN, Nan ,  JUNG, Chang Ho ,  CHEN, Zhiqin

    发明人： CHEN, Nan ,  JUNG, Chang Ho ,  CHEN, Zhiqin

    IPC分类号： G11C7/12 ,  G11C11/409

    CPC分类号： G11C7/12 ,  G11C11/409 ,  G11C2207/005

    摘要： A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage (401,402) in a read column multiplexer. A cross coupled keeper (404) can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the "high" bit line.

    摘要翻译： 针对存储器阵列中的读取路径改进了检测边缘。 实施例通过在读列多路复用器中使用具有较低阈值电压（401,402）的门来提高感测余量。 交叉耦合保持器（404）可以通过增加存储高值的位线上的电压电平来进一步提高感测余量，从而抵消“高”位线上的泄漏。