Abstract:
A system for controlling a bias circuit by sensing RF amplifier output power and compensating for a dominating quiescent bias current includes an amplifier transistor and two sampling transistors. The two sampling transistors are physically smaller than the amplifier transistor, and are preferably the same size. The first sampling transistor is configured to sample the same RF input signal that is amplified by the amplifier transistor. The second sampling transistor is configured to receive and amplify only a bias network signal. The bias network associated with the transistors includes a selection of components based upon operating parameters as well as actual physical sizes of the transistors. The selection of component values in association with transistor sizes is used to enable generation of a current sensing signal that is proportional to the power level of the RF output signal generated by the amplifier transistor. The bias current to the amplifier transistor is controlled by an operational amplifier that is fed with a reference voltage and the dc bias detected by the second small transistor.
Abstract:
The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.
Abstract:
A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.
Abstract:
An envelope tracking power supply (26) and an offset capacitive element (CO) are disclosed. The offset capacitive element (CO) is coupled between a switching output and an analog output of the envelope tracking power supply (26), which operates in one of an envelope tracking mode, a transition mode, and an average power tracking mode. During the envelope tracking mode, the envelope tracking power supply (26) provides an envelope power supply signal using both the switching output and the analog output. During the transition mode, the envelope tracking power supply (26) drives the offset capacitive element (CO) from a first voltage to a second voltage, such that during a transition from the envelope tracking mode to the transition mode, the offset capacitive element (CO) has the first voltage, and during a transition from the transition mode to the average power tracking mode, the offset capacitive element (CO) has the second voltage.
Abstract:
The present disclosure relates to a radio frequency (RF) communications system, which may include any or all of RF modulation and control circuitry, RF power amplifier (PA) circuitry, a direct current (DC)-DC converter, transceiver circuitry, and front-end aggregation circuitry. Embodiments of the RF communications system may relate to reducing cost, reducing size, reducing complexity, increasing efficiency, increasing performance, the like, or any combination thereof.
Abstract:
An envelope tracking power supply and transmitter control circuitry are disclosed. The transmitter control circuitry receives a first envelope power supply control signal and a second envelope power supply control signal. The envelope tracking power supply operates in one of a group of operating modes, which includes a first operating mode and a second operating mode. During both the first operating mode and the second operating mode, a first envelope power supply signal is provided to a driver stage based on the first envelope power supply control signal. During the first operating mode, a second envelope power supply signal is provided to a final stage based on the first envelope power supply control signal. However, during the second operating mode, the second envelope power supply signal is provided to the final stage based on the second envelope power supply control signal.
Abstract:
Radio frequency (RF) transmitter circuitry, which includes an RF power amplifier (PA) and an envelope tracking power supply, is disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using an envelope power supply signal. The envelope tracking power supply provides the envelope power supply signal, which has switching ripple. Further, the envelope tracking power supply operates in either a normal switching ripple mode or a modified switching ripple mode, such that during the normal switching ripple mode, the envelope power supply signal has normal switching ripple, and during the modified switching ripple mode, the envelope power supply signal has modified switching ripple. When the modified switching ripple is required, the envelope tracking power supply operates in the modified switching ripple mode.
Abstract:
An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.
Abstract:
Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a V RAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.
Abstract:
Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.