公开(公告)号：WO2006094197A3

公开(公告)日：2007-01-04

申请号：PCT/US2006007608

申请日：2006-03-03

Applicant: QUALCOMM INC ,  BRIDGES JEFFREY TODD ,  DIEFFENDERFER JAMES NORRIS ,  MCILVAINE MICHAEL SCOTT ,  SARTORIUS THOMAS ANDREW

Inventor： BRIDGES JEFFREY TODD ,  DIEFFENDERFER JAMES NORRIS ,  MCILVAINE MICHAEL SCOTT ,  SARTORIUS THOMAS ANDREW

IPC: G06F1/32

CPC classification number: G06F9/30058 ,  G06F1/3203 ,  G06F1/3275 ,  G06F9/384 ,  Y02D10/13 ,  Y02D10/14

Abstract: A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.

Abstract translation: 描述了一种用于节省电力的重命名寄存器文件。 映射单元将指令寄存器号（IRN）变换为逻辑寄存器号（LRN）。 重命名寄存器文件将LRN映射到物理寄存器编号（PRN），通过直接使用IRN，存在比可寻址的更大数量的物理寄存器。 重命名寄存器文件使用内容可寻址存储器（CAM）来提供映射功能。 重命名寄存器文件CAM还使用当前处理器状态信息来选择性地使标签比较器最小化访问寄存器的功率。 当标签比较器未使能时，它保持在低功率状态。 还描述了使用具有低功率特征的重命名寄存器文件的处理器。

公开(公告)号：WO2006113420A3

公开(公告)日：2006-12-21

申请号：PCT/US2006014042

申请日：2006-04-14

Applicant: QUALCOMM INC ,  SARTORIUS THOMAS ANDREW ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  DOCKSER KENNETH ALAN ,  MCILVAINE MICHAEL SCOTT ,  SMITH RODNEY WAYNE

Inventor： SARTORIUS THOMAS ANDREW ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  DOCKSER KENNETH ALAN ,  MCILVAINE MICHAEL SCOTT ,  SMITH RODNEY WAYNE

IPC: G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

Abstract: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

Abstract translation: 一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便 它无条件地向目标提供输出。 条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。 评估条件。 如果满足条件，则执行操作，并将操作结果输出到目标。 如果条件不满足，则将先前值输出到目标。 后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

公开(公告)号：WO2006130466A2

公开(公告)日：2006-12-07

申请号：PCT/US2006/020440

申请日：2006-05-24

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

Inventor： SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

CPC classification number: G06F9/3844

Abstract: A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

Abstract translation: 微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令， 在分支目标缓存中丢失。 因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。 因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

公开(公告)号：WO2006113420A2

公开(公告)日：2006-10-26

申请号：PCT/US2006/014042

申请日：2006-04-14

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

Inventor： SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

IPC: G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

Abstract: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

Abstract translation: 被构造为接收一个或多个操作数作为输入的条件指令，如果满足条件则向目标输出对操作数执行的操作的结果，并且如果条件满足则不提供输出 不满意，被执行以便无条件地向目标提供输出。 条件指令获取目标的先前值（即，由更新该目标的条件指令之前的最近指令产生的值）。 条件被评估。 如果条件满足，则执行操作并将操作的结果输出到目标。 如果条件不满足，则将先前值输出到目标。 在条件评估之前，后续指令可能依赖目标作为操作数源（无论写入寄存器还是转发给指令）。

公开(公告)号：WO2006102665A2

公开(公告)日：2006-09-28

申请号：PCT/US2006/011172

申请日：2006-03-23

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris

Inventor： SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

Abstract translation: 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中的任何复制条目是否包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含修改的数据，则从内存中读取的数据将被写入所选条目，而无需先阅读条目。 在银行缓存中，两个或更多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否提高了处理器性能并降低了功耗。

公开(公告)号：WO2006086713A3

公开(公告)日：2006-08-17

申请号：PCT/US2006/004892

申请日：2006-02-10

Applicant: QUALCOMM INCORPORATED ,  MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

Inventor： MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

IPC: G06F9/38 ,  G06F9/318

Abstract: Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.

公开(公告)号：WO2011142967A1

公开(公告)日：2011-11-17

申请号：PCT/US2011/034095

申请日：2011-04-27

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew

Inventor： SARTORIUS, Thomas, Andrew

IPC: G06F9/34 ,  G06F9/35 ,  G06F9/445 ,  G06F12/10 ,  G06F13/28

CPC classification number: G06F9/34 ,  G06F9/35 ,  G06F12/1027 ,  G06F12/1081 ,  Y02D10/13

Abstract: Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.

Abstract translation: 描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。 在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。 数据值可以转换为第一个物理地址。 虚拟地址可以转换为第二个物理地址。 第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。

公开(公告)号：WO2011022493A1

公开(公告)日：2011-02-24

申请号：PCT/US2010/045910

申请日：2010-08-18

Applicant: QUALCOMM INCORPORATED ,  STEMPEL, Brian M. ,  DIEFFENDERFER, James N. ,  SARTORIUS, Thomas A. ,  MANDZAK, David J. ,  SMITH, Rodney W.

Inventor： STEMPEL, Brian M. ,  DIEFFENDERFER, James N. ,  SARTORIUS, Thomas A. ,  MANDZAK, David J. ,  SMITH, Rodney W.

IPC: G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/3832 ,  G06F9/3844 ,  G06F9/3861

Abstract: Efficient techniques are described for not executing an issued conditional non-branch instruction. A conditional non-branch instruction is identified as being eligible for a prediction, the prediction indicating that the eligible conditional non-branch (ECNB) instruction would not execute. The ECNB instruction executes as a no operation (NOP) instruction in response to the prediction that the ECNB instruction would not execute. A source operand required for the ECNB instruction to execute is not fetched in response to the prediction to not execute.

Abstract translation: 描述了不执行发出的条件非分支指令的高效技术。 条件非分支指令被识别为有资格进行预测，该预测指示合格条件非分支（ECNB）指令将不执行。 响应于ECNB指令不执行的预测，ECNB指令作为无操作（NOP）指令执行。 ECNB指令执行所需的源操作数不响应于不执行的预测而被取出。

公开(公告)号：WO2008039947A1

公开(公告)日：2008-04-03

申请号：PCT/US2007/079781

申请日：2007-09-27

Applicant: QUALCOMM Incorporated ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Micheal ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

Inventor： SMITH, Rodney Wayne ,  STEMPEL, Brian Micheal ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/30058 ,  G06F9/3844 ,  G06F9/3861

Abstract: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.

Abstract translation: 公开了一种在预测分支指令验证之前解决同步分支预测的方法。 该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。 该方法还包括选择一个校正状态。 如果预测的分支指令之一被错误预测，则所选择的校正状态用于指导未来的指令提取。

公开(公告)号：WO2008028103A2

公开(公告)日：2008-03-06

申请号：PCT/US2007/077340

申请日：2007-08-31

Applicant: QUALCOMM Incorporated ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian ,  SARTORIUS, Thomas Andrew ,  SMITH, Wayne

Inventor： DIEFFENDERFER, James Norris ,  STEMPEL, Brian ,  SARTORIUS, Thomas Andrew ,  SMITH, Wayne

CPC classification number: G06F9/3844 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/322 ,  G06F9/3806

Abstract: An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.

Abstract translation: 公开了一种用于模拟显式子程序调用的分支预测行为的装置。 该装置包括被配置为接收指令地址和第二输入的第一输入。 第二输入被配置为接收描述与子程序的隐式子程序调用有关的指令地址的预解码信息。 响应于预解码信息，该装置还包括加法器，其被配置为向定义返回地址的指令地址添加常数，使得将返回地址存储到显式子例程资源，从而便于后续分支预测返回呼叫 指令。