公开(公告)号：WO2006113570A3

公开(公告)日：2007-02-15

申请号：PCT/US2006014318

申请日：2006-04-13

Applicant: INTEL CORP ,  ROSENBLUTH MARK ,  NARAD CHARLES

Inventor： ROSENBLUTH MARK ,  NARAD CHARLES

IPC: G06F5/10 ,  G06F12/00

CPC classification number: G06F5/10 ,  G06F12/0831

Abstract: The disclosure describes techniques used by one or more producers and consumers of one or more rings.

Abstract translation: 本公开描述了一个或多个环的一个或多个生产者和消费者使用的技术。

公开(公告)号：WO2005066798A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/043425

申请日：2004-12-23

Applicant: INTEL CORPORATION ,  MATTINA, Matthew ,  CHRYSOS, George, Z.

Inventor： MATTINA, Matthew ,  CHRYSOS, George, Z.

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084

Abstract: The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.

Abstract translation: 本申请是用于在CMP中维持高速缓存一致性的协议。 CMP设计包含多个处理器内核，每个内核都有自己的私有缓存。 此外，CMP具有单个在船共享缓存。 处理器核心和共享高速缓存可以与同步的，无缓冲的双向环互连连接在一起。 在本协议中，在环上发送单个INVALIDATEANDACKNOWLEDGE消息以使特定核心无效并且确认特定核心。

公开(公告)号：WO2005029335A2

公开(公告)日：2005-03-31

申请号：PCT/US2004/029687

申请日：2004-09-10

Applicant: INTEL CORPORATION

Inventor： GILBERT, Jeffrey ,  CHENG, Kai

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0831 ,  G06F2212/507

Abstract: A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache coherency state. The joint cache coherency state may have a first state for the inner interface and a second state for the outer interface, where the second state has higher privilege than the first state. In one embodiment this may promote speculative invalidation. In other embodiments this may reduce snoop transactions on the inner interface.

Abstract translation: 公开了一种用于高速缓存一致性状态的方法和装置。 在一个实施例中，跨两个接口（内部接口和外部接口）可访问的缓存可具有联合缓存一致性状态。 联合高速缓存一致性状态可以具有用于内部接口的第一状态和用于外部接口的第二状态，其中第二状态具有比第一状态更高的特权。 在一个实施例中，这可能促使推测失效。 在其他实施例中，这可以减少内部接口上的窥探交易。

公开(公告)号：WO2005001693A3

公开(公告)日：2005-03-31

申请号：PCT/EP2004050878

申请日：2004-05-25

Applicant: IBM ,  IBM UK ,  HELLER THOMAS ,  BAUM RICHARD ,  IGNATOWSKI MICHAEL ,  RYMARCZYK JAMES

Inventor： HELLER THOMAS ,  BAUM RICHARD ,  IGNATOWSKI MICHAEL ,  RYMARCZYK JAMES

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0824

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a hypervisor.

Abstract translation: 多处理器计算机系统具有多个处理节点，这些处理节点使用处理器状态信息来确定系统中的哪些相干高速缓存需要检查由单个始发处理器的存储请求产生的一致性事务。 计算机的节点具有动态一致性边界，使得硬件在任何特定时间点仅使用大系统中的全部处理器的子集用于单个工作负载，并且可以随着监控软件或固件扩展和合同而优化高速缓存一致性 正在用于运行任何单个工作负载的处理器数量。 一个节点的多个实例可以连接到一个二级控制器来创建一个大的多处理器系统。 节点控制器使用模式位来确定哪些处理器必须接收节点控制器接收到的任何给定事务。 第二级控制器使用模式位来确定哪些节点必须接收由第二级控制器接收的任何给定事务。 逻辑分区映射到允许的物理处理器。 包含系统中处理器和高速缓存总数的子集的高速缓存一致性区域被选择用于它们的物理接近度。 可以使用管理程序为每个分区定义不同的高速缓存一致性区域。

公开(公告)号：WO2005017755A1

公开(公告)日：2005-02-24

申请号：PCT/US2004/024685

申请日：2004-07-29

Applicant: NEWISYS, INC. ,  GLASCO, David, B.

Inventor： GLASCO, David, B.

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/082

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. If information for responding to a request is available in a remote data cache, a response with a completion indicator is provided to the requesting processor. The completion indicator allows the request to be met without having to probe local or remote nodes.

Abstract translation: 根据本发明，提供了用于提高多处理器，多集群系统中的数据访问效率的方法和装置。 允许各种事务在本地完成的机制通过提供与系统中的各种群集相关联的远程数据高速缓存来实现。 远程数据高速缓存接收远程集群中存储线路的数据和状态信息。 如果用于响应请求的信息在远程数据高速缓存中可用，则具有完成指示符的响应被提供给请求处理器。 完成指示器允许满足请求，而无需探测本地或远程节点。

公开(公告)号：WO2004061678A3

公开(公告)日：2005-02-03

申请号：PCT/US0338347

申请日：2003-12-03

Applicant: INTEL CORP

Inventor： HUM HERBERT ,  GOODMAN JAMES A

IPC: G06F12/08

CPC classification number: G06F12/0822 ,  G06F12/0813 ,  G06F12/0831

Abstract: Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that designates a single copy of data from which further copies can be made. A cache line in the F state is used to respond to request for a copy of the cache line. In one embodiment, the newly created copy is placed in the F state and the cache line previously in the F state is put in the Shared (S) state, or the Invalid (I) state. Thus, if the cache line is shared, one shared copy is in the F state and the remaining copies of the cache line are in the S state.

Abstract translation: 这里描述了具有五种状态的高速缓存一致性协议：修改，独占，共享，无效和转发（MESIF）。 MESIF高速缓存一致性协议包括转发（F）状态，其指定可以进行进一步复制的数据的单个副本。 处于F状态的高速缓存行用于响应对高速缓存行的副本的请求。 在一个实施例中，新创建的副本被置于F状态，并且先前处于F状态的高速缓存行被置于共享（S）状态或无效（I）状态。 因此，如果高速缓存行被共享，则一个共享副本处于F状态，并且高速缓存行的剩余副本处于S状态。

公开(公告)号：WO02001366A2

公开(公告)日：2002-01-03

申请号：PCT/US2001/018683

申请日：2001-06-07

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0831

Abstract: The invention provides a cache management system comprising in various embodiment pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache line recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract translation: 本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。 本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中 记录在无效历史表中的高速缓存行的行地址。 在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从 所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

公开(公告)号：WO0008564A8

公开(公告)日：2000-04-27

申请号：PCT/US9917040

申请日：1999-07-27

Applicant: INTEL CORP ,  NEIGER GILBERT A ,  WADE NICHOLAS D ,  CHENG KAI

Inventor： NEIGER GILBERT A ,  WADE NICHOLAS D ,  CHENG KAI

IPC: G06F12/08 ,  G06F15/177 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0813 ,  G06F12/0831

Abstract: In some embodiments, a computer system includes nodes (N0, N1, N2, N3) connected through conductors (22, 24, 26, 28). At least some of the nodes include memory (46) and processing circuitry (66) to receive snoop requests in a node reception order and to initiate snoops of the memory in the node before the snoop requests are in global order. The at least some nodes also include an ordering buffer (62) to receive the snoop requests and provide them at an output of the ordering buffer in the global order.

Abstract translation: 在一些实施例中，计算机系统包括通过导体（22,24,26,28）连接的节点（N0，N1，N2，N3）。 节点中的至少一些包括存储器（46）和处理电路（66），以在节点接收顺序中接收窥探请求，并且在窥探请求处于全局顺序之前发起节点中的存储器的窥探。 至少一些节点还包括排序缓冲器（62），用于接收窥探请求，并以全局顺序在排序缓冲器的输出端提供它们。

公开(公告)号：WO1999032955A2

公开(公告)日：1999-07-01

申请号：PCT/US1997023636

申请日：1997-12-19

Applicant: BULL HN INFORMATION SYSTEMS INC.

Inventor： BULL HN INFORMATION SYSTEMS INC. ,  SHELLY, William, A. ,  INOSHITA, Minoru ,  BARYLA, Robert, J.

IPC: G06F00/00

CPC classification number: G06F12/0859 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.

Abstract translation: 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：用于识别驻留在高速缓冲存储器中的信息块的处理器目录，用于识别来自CPU的请求上的高速缓存未命中的逻辑，用于存储错过块的标识的高速缓存未命中输出缓冲器 以及要从高速缓冲存储器移出的块以便为所请求的块腾出空间，并且用于选择性地将标识发送到CPU总线上，用于存储所有最近错过的块的标识的高速缓存未命中输入缓冲堆栈和要从所有块中交换的块的标识 组中的CPU，用于将高速缓存未命中输出缓冲器堆栈中的标识与高速缓存未命中输入缓冲器堆栈和控制逻辑中的标识进行比较的比较器，响应于第一比较器感测到比较（指示另一CPU对于 块被交换），用于禁止将交换要求广播到CPU总线上，并将交换操作转换为“虹吸” 操作来服务其他CPU的请求。

公开(公告)号：WO99014676A1

公开(公告)日：1999-03-25

申请号：PCT/US1998/019342

申请日：1998-09-16

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0831

Abstract: The processor (20) includes at least a lower (110, 120) and a higher (140) level non-inclusive cache, and a system bus controller (100). The system bus controller (100) snoops commands on the system bus (30), and supplies the snooped commands to each level of cache (110, 120, 140). Additionally, the system bus controller (100) receives the response to the snooped command from each level of cache (110, 120, 140), and generates a combined response thereto. When generating responses to the snooped command, each lower level cache (110, 120) supplies its responses to the next higher level cache (120, 140). Higher level caches (120, 140) generate their responses to the snooped command based in part upon the response of the lower level caches (110, 120). Also, high level caches (120, 140) determine whether or not the cache address, to which the real address of the snooped command maps, matches the cache address of at least one previous high level cache query. If a match is found by a high level cache (120, 140), then the high level cache (120, 140) generates a retry response to the snooped command, which indicates that the snooped command should be resent at a later point in time, in order to prevent a collision between cache queries.

Abstract translation: 处理器（20）包括至少一个较低（110,120）和更高（140）级的非包容性高速缓存，以及一个系统总线控制器（100）。 系统总线控制器（100）在系统总线（30）上窥探命令，并将窥探的命令提供给每个级别的高速缓存（110,120,140）。 另外，系统总线控制器（100）从高速缓存（110,120,140）的每个级别接收对窥探命令的响应，并且产生对其的组合响应。 当产生对窥探命令的响应时，每个下级高速缓存（110,120）将其响应提供给下一个较高级别的高速缓存（120,140）。 部分基于较低级别高速缓存（110,120）的响应，较高级别高速缓存（120,140）生成对窥探命令的响应。 此外，高级别高速缓存（120,140）确定被窥探命令的真实地址映射到的高速缓存地址是否与至少一个先前的高级别高速缓存查询的高速缓存地址相匹配。 如果由高级缓存（120,140）找到匹配，则高级缓存（120,140）生成对窥探命令的重试响应，其指示在随后的时间点重新发送被窥探的命令 ，以防止缓存查询之间的冲突。