公开(公告)号：WO01054279A1

公开(公告)日：2001-07-26

申请号：PCT/US2001/001792

申请日：2001-01-20

IPC分类号： G11C11/16 ,  H03K3/356 ,  H03K3/45 ,  H03K17/687 ,  H03K17/693 ,  H03K19/177

CPC分类号： G11C11/16 ,  H03K3/356008 ,  H03K3/45 ,  H03K17/6871 ,  H03K17/693

摘要： The invention generally relates to registers or flip-flop circuits. More particularly, the present invention refers to the use of non-volatile ferromagnetic memory cell to store binary data in a register or flip-flop circuit. It is an advantage of the invention to have a flip-flop (10) with a ferromagnetic memory cell (1) or bit to store data even when there is no power provided to the circuitry. Thus, saving power during operation of any associated circuitry, and ensuring that there is no loss of data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, or eliminating "write fatigue". The invention provides a latching circuit, comprising an input line (21) entering the latching circuit for receiving a signal, an output line, electrically coupled to the input line, for outputting the signal, and a ferromagnetic bit (1) and sensor coupled between the input line and the output line, to store a form of the signal in the ferromagnetic bit even when power has been suspended to the latching circuit.

摘要翻译： 本发明涉及寄存器或触发电路。 更具体地说，本发明涉及用于在寄存器或触发电路中存储二进制数据的非易失性铁磁存储器单元的用途。 与单元（1）或铁磁存储器位相关联的触发器（10）即使在电路未接收到电源时也是有利的，这允许在任何相关电路的操作期间节省能量，并确保防止任何损失。 在发生暂时的电力故障时。 此外，铁磁单元允许对数据进行无限次数的切换动作而不改变所述单元中的数据存储容量，并且可以消除写入疲劳。 本发明还涉及一种锁定电路，该锁定电路包括穿过锁定电路以接收信号的输入线（21），电耦合到输入线以输出信号的输出线。 ，以及耦合在输入线和输出线之间的铁磁比特（1）和检测器，用于即使当锁存电路的供电已被暂停时，也在铁磁比特中存储信号的形状。

公开(公告)号：WO01035640A2

公开(公告)日：2001-05-17

申请号：PCT/US2000/030976

申请日：2000-11-10

IPC分类号： H03K17/693 ,  H04N5/268 ,  H03K17/06

CPC分类号： H03K17/693 ,  H04N5/268

摘要： A signal switching device (2) has a switch assembly (14) with a plurality of inputs (4, 6, 8, 10) for connection to respective signal sources and at least one signal output (16) for connection to an output device. The switch assembly has a plurality of passive switches each connected at one end to a respective one of the signal inputs and at the other end to an output connected to the signal output. A micro-controller (24) is connected to the switch assembly for turning on the switches sequentially in a predetermined order and for predetermined intervals of time, such that only one switch is on at any one time, and the input signals are repeatedly provided in a predetermined sequence to the signal output.

摘要翻译： 信号切换装置（2）具有开关组件（14），其具有多个用于连接到相应信号源的输入端（4,6,8,10）和用于连接到输出装置的至少一个信号输出端（16）。 开关组件具有多个无源开关，每个无源开关一端连接到信号输入端的相应一端，另一端连接到与信号输出相连的输出端。 微控制器（24）连接到开关组件，用于以预定的顺序依次接通开关并且以预定的时间间隔，使得在任何一个时间只有一个开关接通，并且输入信号被重复地设置在 对信号输出的预定顺序。

公开(公告)号：WO00069071A1

公开(公告)日：2000-11-16

申请号：PCT/US2000/007422

申请日：2000-03-21

IPC分类号： H03K17/041 ,  H03K17/693 ,  H03K19/018 ,  H04L25/02 ,  H03K19/0175

CPC分类号： H04L25/0282 ,  H03K17/04106 ,  H03K17/693 ,  H03K19/01831 ,  H04L25/0276 ,  H04L25/029

摘要： An integrated circuit driver (165A, 165B) provides, among other things, a high data communication rate, a large common mode output voltage range, avoidance of spikethrough current that increases power consumption, improved switching speed using current-steering techniques, and improved matching of steady-state output current in the high logic state to that of the low logic state. The driver (165A, 165B) includes complementary differential pairs (212, 214) and associated current mirror circuits (216, 222) that differentially source/sink current at a pair of load conductors (110A, 110B) to drive the load conductors (110A, 110B) into a logic state. A single-ended embodiment is also described.

摘要翻译： 集成电路驱动器（165A，165B）提供了高数据通信速率，大的共模输出电压范围，避免增加功耗的快速消耗电流，使用电流转向技术提高的开关速度以及改进的匹配 在高逻辑状态下的稳态输出电流为低逻辑状态。 驱动器（165A，165B）包括互补差分对（212,214）和相关联的电流镜电路（216,222），其在一对负载导体（110A，110B）处差分地源/吸收电流以驱动负载导体 ，110B）变为逻辑状态。 还描述了单端实施例。

公开(公告)号：WO00022730A1

公开(公告)日：2000-04-20

申请号：PCT/EP1999/007531

申请日：1999-10-07

IPC分类号： H03K17/16 ,  H03K17/693

CPC分类号： H03K17/162 ,  H03K17/693

摘要： A multiplexer circuit (100) comprises at least two input channels (IN0, IN1) and an output channel (2), each input channel (IN0, IN1) comprising a first transmission gate (FT0, FT1) which can be switched by a select signal (SELECT0, SELECT0 ; SELECT1, SELECT1 ) for connecting the input channel (IN0, IN1) to the output channel (2), and wherein at least one of the input channels (IN0, IN1) comprises a bypass circuit for preventing a current flowing through the first transmission gate (FT0, FT1) from reaching the other input channel, and a second transmission gate (ST0, ST1).

摘要翻译： 多路复用器电路（100）包括至少两个输入通道（IN0，IN1）和输出通道（2），每个输入通道（IN0，IN1）包括可通过选择切换的第一传输门（FT0，FT1） 用于将输入通道（IN0，IN1）连接到输出通道（2）的信号（SELECT0， SELECT0 ; SELECT1， SELECT1 ），并且其中至少一个输入 通道（IN0，IN1）包括用于防止流过第一传输门（FT0，FT1）的电流到达另一输入通道的旁路电路和第二传输门（ST0，ST1）。

公开(公告)号：WO98045946A1

公开(公告)日：1998-10-15

申请号：PCT/US1998/006902

申请日：1998-04-06

IPC分类号： H03K17/693 ,  H03M1/10 ,  H03M1/12 ,  H03M1/80 ,  H03M3/02 ,  H03K17/56 ,  H03B5/36

CPC分类号： H03M1/1061 ,  H03K17/693 ,  H03M1/804

摘要： A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1...7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

摘要翻译： 可编程集成电路电容器阵列包括多个二次加权电容器（16）和多个开关（18），其选择性地在第一和第二端子之间并联电容器。 控制电路（10）结合多个调整输入（TR0,1）和符号输入（TRS）响应多个电容选择输入（CS0,1,2），以产生多个选择信号（SEL0 ，1 ... 7）连接在开关的控制电极上以耦合一个或多个电容器，从而提供第一和第二端子之间的期望电容的精确值，尽管每单位面积的电容量有任何制造偏差。

公开(公告)号：WO1996023356A1

公开(公告)日：1996-08-01

申请号：PCT/DE1995001875

申请日：1995-12-29

申请人： SIEMENS AKTIENGESELLSCHAFT ,  HANNEBERG, Armin ,  TEMPEL, Georg

发明人： SIEMENS AKTIENGESELLSCHAFT

IPC分类号： H03K17/10

CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C16/12 ,  G11C16/14 ,  H03K3/356017 ,  H03K3/356147 ,  H03K17/102 ,  H03K17/693

摘要： The invention concerns a MOS circuit for switching high voltages on a semiconductor chip. In order to switch a high negative voltage (-Vpp), for example as a programming voltage on the word line of a flash-memory, two circuit variants are given which are formed only with transistors of the same type of conduction as the substrate. In this way it is possible to dispense with deep insulating tanks which require special technology.

摘要翻译： 用于切换高的负电压（-VPP），例如作为一个编程电压施加到快闪存储器的字线，被指定两种类型的电路装置，其与晶体管为同一导电类型的衬底上形成。 这使得有可能与需要特殊工艺深水井绝缘免除。

公开(公告)号：WO1995008868A1

公开(公告)日：1995-03-30

申请号：PCT/US1994010335

申请日：1994-09-16

申请人： MICREL, INC.

发明人： MICREL, INC. ,  MOYER, James, C. ,  BITTNER, Harry, J.

IPC分类号： H03K03/353

CPC分类号： H01L29/7816 ,  H01L27/088 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/78 ,  H03K17/08142 ,  H03K17/693 ,  H03K2217/0018

摘要： To avoid forward biasing the diodes within an N-channel transistor, the body (36) and source (38) of the N-channel transistor (34) are switchably connected via a high-voltage FET (42). The gates (46, 50) of the N-channel transistor (34) and high-voltage transistor (42) are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor (42) shorts the body (36) and source (38) of the N-channel transistor (34). When both transistors are off, the body (36) and source (38) of the N-channel transistor (34) are disconnected and a third transistor (56) couples the body to a reference potential. The N-channel transistor (34) and high voltage transistor (42) share a common body in a semiconductor substrate. The source (38) of the N-channel transistor (34) provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.

摘要翻译： 为了避免在N沟道晶体管内向前偏置二极管，N沟道晶体管（34）的主体（36）和源极（38）通过高压FET（42）可切换地连接。 N沟道晶体管（34）和高电压晶体管（42）的栅极（46,50）连接在一起，使得两个晶体管同时导通或截止。 当两个晶体管导通时，高压晶体管（42）使N沟道晶体管（34）的主体（36）和源极（38）短路。 当两个晶体管都断开时，N沟道晶体管（34）的主体（36）和源极（38）被断开，第三晶体管（56）将本体耦合到参考电位。 N沟道晶体管（34）和高压晶体管（42）在半导体衬底中共享公共体。 N沟道晶体管（34）的源极（38）为电路提供输出端子。 每个连接到不同电源电压的这些设备可以连接到相同的输出端子并选择性地通电以形成电压复用器。

公开(公告)号：WO1994022664A1

公开(公告)日：1994-10-13

申请号：PCT/JP1993000440

申请日：1993-04-05

申请人： CMET, INC. ,  YAC CORPORATION ,  NARUKAWA, Hidetaka ,  SAITO, Naoichiro ,  HAYANO, Seiji ,  TANI, Kazunori ,  NARUO, Hatsumi ,  SARADA, Ichitaro

发明人： CMET, INC. ,  YAC CORPORATION

IPC分类号： B29C67/00

CPC分类号： H03K17/693 ,  B29C41/12 ,  B29C64/124 ,  B29C64/386 ,  B29C2037/90 ,  H01L29/1087 ,  H01L29/78 ,  H01L29/7801 ,  H03K17/08142 ,  H03K2217/0018

摘要： A photohardening molding apparatus for forming a hardened layer having a controlled contour by applying light, the irradiation region of which is controlled, to the surface of a photosetting liquid, precipitating the hardened layer, and repeating the step of recoating the upper surface of the hardened layer with an unhardened liquid while making a recoater travel on the hardened layer, wherein the recoater travelling stroke is restricted to a required minimum level so as to reduce the recoating time. To achieve this object, a means for determining minimum and maximum coordinates of the contour of each section is added, whereby a recoater travelling stroke is restricted to within the coordinates.

摘要翻译： 一种光硬化成型装置，其特征在于，通过将照射区域进行控制的光照射到光固化液的表面上，形成具有受控轮廓的硬化层，使硬化层析出，重复上述硬化层 层，同时在硬化层上进行再涂布行进，其中重涂器行进行程被限制到所需的最小水平，以便减少重新涂覆时间。 为了实现该目的，添加了用于确定每个部分的轮廓的最小和最大坐标的装置，由此将重涂器行进冲程限制在坐标内。

公开(公告)号：WO1990006659A1

公开(公告)日：1990-06-14

申请号：PCT/US1989005490

申请日：1989-12-05

申请人： TRANSWITCH CORPORATION

发明人： TRANSWITCH CORPORATION ,  UPP, Daniel, C.

IPC分类号： H04Q03/42

CPC分类号： H04Q11/04 ,  H03K17/693 ,  H04J3/0685

摘要： A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size. The use of multiple stages is permitted as the clock regeneration means associated with each port prevents signal dispersion and signal clock skew. The passing and switching of clock signals along with the data also permits the switching matrix to simultaneously handle lines having different rates, provided that a line of a given rate which is an input to the switching network must be connected to another line of the same rate which is an output of the switching network.

公开(公告)号：WO2017062142A1

公开(公告)日：2017-04-13

申请号：PCT/US2016/051712

申请日：2016-09-14

申请人： MICROCHIP TECHNOLOGY INC.

发明人： KO, Isaac ,  HO, Ka, Wai ,  CHAN, Wan, Tim

IPC分类号： H03K17/687 ,  H04B1/48

CPC分类号： H03K17/693 ,  H03K17/6874 ,  H04B1/48

摘要： An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.

摘要翻译： 公开了一种用于超声弹性成像探针的改进的模拟开关。 与现有技术的模拟开关相比，改进的模拟开关导致更少的散热。