公开(公告)号：WO2013147801A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031249

申请日：2012-03-29

Applicant: INTEL CORPORATION ,  VARMA, Ankush ,  SISTLA, Krishnakanth ,  QUIROZ, Cesar ,  GARG, Vivek ,  ROWLAND, Martin ,  SODHI, Inder ,  BURNS, James

Inventor： VARMA, Ankush ,  SISTLA, Krishnakanth ,  QUIROZ, Cesar ,  GARG, Vivek ,  ROWLAND, Martin ,  SODHI, Inder ,  BURNS, James

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

Abstract translation: 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高的峰值性能。

公开(公告)号：WO2017171893A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025789

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： NAIR, Vijay K. ,  MALATKAR, Pramod

IPC: H01L23/552 ,  H01L23/48

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed.

Abstract translation: 根据所公开的实施例，提供了用于实现具有用于RF集成的EMI屏蔽的有机加强件的方法，系统和设备。 例如，根据一个实施例，存在一种装置，其中具有：其中具有电迹线和接地平面的衬底层; 与所述衬底层的电迹线电接合的功能半导体管芯; 与功能半导体管芯的顶表面热接合的热管; 一个或多个有机介电材料的中介层，电连接到基底层的接地平面并电连接到热管; 其中所述一个或多个中介层形成所述电磁屏蔽以电屏蔽所述功能半导体管芯; 并且进一步地，其中形成有机加强件的一个或多个中介层将机械地保持平面形式的基底层。 披露了其他相关的实施例。

公开(公告)号：WO2017171889A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025779

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： MUTHUR SRINATH, Purushotham Kaushik ,  MALATKAR, Pramod ,  AGRAHARAM, Sairam ,  JHA, Chandra M. ,  CHOUDHURY, Arnab ,  RARAVIKAR, Nachiket R.

IPC: H01L23/12 ,  H01L23/48

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

Abstract translation: 根据所公开的实施例，提供了用于实现3D封装的热解决方案的方法，系统和设备。 例如，根据一个实施例，存在一种设备，其中具有：其中具有电迹线的衬底层; 与所述衬底层的电迹线电接合的第一层功能硅芯片，所述第一层功能硅芯片具有集成在其上的第一热衬垫; 位于所述第一层功能硅晶粒上方的第二层功能硅晶粒，所述第二层功能硅晶粒具有集成于其上的第二导热垫; 以及位于所述第一层功能硅管芯和所述第二层功能硅管芯之间的导电层，其中所述导电层用于：（i）将所述第二层功能硅管芯电连接到所述第一层功能硅管芯和（ii） 第一层功能硅的第一导热焊盘通过焊料与第二层功能硅芯片的第二导热焊盘相接合。 披露了其他相关的实施例。

公开(公告)号：WO2017171880A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025749

申请日：2016-04-01

Applicant: INTEL CORPORATION ,  TIEN, Ming-Chun ,  JEONG, Seongtae ,  GRUNES, Harsha

Inventor： TIEN, Ming-Chun ,  JEONG, Seongtae ,  GRUNES, Harsha

IPC: H01L21/027 ,  G03F7/20

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing critical dimension (CD) and phase calibration of alternating phase shift masks (APSM) and chromeless phase lithography (CPL) masks for modeling. For instance, in accordance with one embodiment, there are means described for identifying critical dimensions of structures of a mask via means for illuminating the mask via a light source; collecting multiple measurements of the critical dimensions of the structures of the mask by iteratively: (i) capturing a diffraction pattern from diffraction of the illumination traversing through the mask for each of multiple structures of the mask at different focus offsets, and (ii) measuring a difference in width between neighboring spaces in the diffraction patterns for each of the multiple structures of the mask at the different focus offsets; curve fitting the collected multiple measurements against target physical critical dimensions for each of the multiple structures to determine a critical dimension delta between the target physical measurements and the collected multiple measurements; and analyzing the critical dimension delta to extract constructive lateral dimensions and effective trench depths for each of the multiple structures of the mask. Other related embodiments are disclosed.

Abstract translation: 根据所公开的实施例，提供了用于实现交替相移掩模（APSM）和无铬相位光刻（CPL）掩模的临界尺寸（CD）和相位校准的方法，系统和设备， 造型。 例如，根据一个实施例，描述了用于经由用于经由光源照射掩模的装置来识别掩模的结构的临界尺寸的装置; 通过迭代地收集掩模结构的临界尺寸的多个测量结果：（i）在不同的焦点偏移下，针对掩模的多个结构中的每一个从穿过掩模的照明的衍射捕获衍射图案，以及（ii）测量 在不同的焦点偏移处，针对掩模的多个结构中的每一个的衍射图案中的相邻空间之间的宽度差; 将所收集的多个测量值与所述多个结构中的每一个的目标物理临界尺寸进行曲线拟合，以确定所述目标物理测量值与所述收集的多个测量值之间的临界尺寸增量; 以及分析临界尺寸δ以提取掩模的多个结构中的每一个的构造性横向尺寸和有效沟槽深度。 披露了其他相关的实施例。

公开(公告)号：WO2017171879A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025747

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： LAI, Min-Tih ,  CAI, Yuhong

IPC: H01L23/48 ,  H01L23/34

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a stress distribution interposer for mitigating substrate cracking. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate having electrical traces therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate; an interposer bonded at a bottom surface to the substrate and bonded at a top surface to the functional semiconductor die; and in which the interposer includes edges with a coefficient of thermal expansion and modulus which is between a coefficient of thermal expansion and modulus of the substrate and a coefficient of thermal expansion and modulus of the functional semiconductor die. Other related embodiments are disclosed.

Abstract translation: 根据所公开的实施例，提供了用于实现用于减轻基板开裂的应力分布内插器的方法，系统和设备。 例如，根据一个实施例，存在一种设备，其中具有：其中具有电迹线的衬底; 与所述衬底的所述电迹线电接合的功能半导体管芯; 中介层，所述中介层在底表面处结合到所述衬底并且在顶表面处结合到所述功能半导体管芯; 并且其中所述内插器包括边缘，所述边缘的热膨胀系数和模量在所述基板的热膨胀系数和模量之间以及所述功能半导体芯片的热膨胀系数和模量之间。 披露了其他相关的实施例。

公开(公告)号：WO2017112875A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/068342

申请日：2016-12-22

Applicant: ARIZONA TECHNOLOGY ENTERPRISES

Inventor： SHERBECK, Jonathan

IPC: F25B11/02 ,  F25B9/14 ,  F25B9/08 ,  F25B9/06 ,  F22B3/02 ,  F25B19/00 ,  F25B41/04 ,  F25B49/00

CPC classification number: F22B3/02

Abstract: In accordance with embodiments disclosed herein, there are provided methods and systems for implementing a closed low grade heat driven Rankine cycle driving a reverse Brayton cycle using an ejector with a liquid desiccant loop to produce shaft power and refrigeration by adiabatic expansion and evaporation (the Sherbeck cycle). For example, in one embodiment, such a system includes means for converting input heat energy into output rotational shaft power, wherein such means include at least means for evaporating a refrigerant in a first gas; means for receiving the input heat energy at a vapor generator having the first fluid therein; means for vaporizing the first fluid at the vapor generator to create high pressure vapor; means for ejecting the high pressure vapor through an ejector to create a low pressure by drawing the first gas through a turbine; means for driving an alternator through Adiabatic expansion of the first gas in the turbine to output the rotational shaft power from the alternator; means for condensing the first gas via condenser, wherein the first gas flows through a separator before cycling back into the turbine and further wherein the refrigerant flows returns to the boiler feedwater pump drawn by the low pressure through an expansion component and into an evaporator; and means for cycling the first gas which is saturated with the refrigerant from the condenser through a dryer via a sorbent loop to dry the first gas. Other related embodiments are described.

Abstract translation: 根据本文所公开的实施例，提供了用于实现使用具有液体干燥剂回路的喷射器来驱动逆向布雷顿循环的封闭低等级热驱动朗肯循环来产生轴功率和制冷的方法和系统 通过绝热膨胀和蒸发（谢贝克循环）。 例如，在一个实施例中，这样的系统包括用于将输入热能转换为输出旋转轴功率的装置，其中这种装置至少包括用于蒸发第一气体中的制冷剂的装置; 用于在其中具有第一流体的蒸汽发生器处接收输入热能的装置; 用于蒸发蒸汽发生器处的第一流体以产生高压蒸汽的装置; 用于通过喷射器喷射高压蒸汽以通过将第一气体抽吸通过涡轮而产生低压的装置; 用于通过涡轮机中的第一气体的绝热膨胀驱动交流发电机以从交流发电机输出旋转轴动力的装置; 用于经由冷凝器冷凝所述第一气体的装置，其中所述第一气体在循环回所述涡轮机之前流过分离器，并且其中所述制冷剂流返回到所述锅炉给水泵，所述锅炉给水泵由所述低压通过膨胀组件并且进入蒸发器; 以及用于使来自冷凝器的制冷剂饱和的第一气体循环经过吸附剂回路的干燥器以干燥第一气体的装置。 描述了其他相关的实施例。

公开(公告)号：WO2013147854A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031478

申请日：2012-03-30

Applicant: INTEL CORPORATION ,  GOGLIN, Stephen D.

Inventor： GOGLIN, Stephen D.

IPC: G06F1/32 ,  G06F1/16

CPC classification number: H04W52/0225 ,  G01S19/34 ,  G06F1/3206 ,  G06F1/325 ,  H04W4/02 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164

Abstract: In accordance with embodiments disclosed herein, there are provided systems, apparatuses, and methods for saving GPS power by detecting indoor use. For example, in one embodiment, such means may include means for receiving a first reading of light within a visible spectrum of electromagnetic radiation; means for receiving a second reading of light within an infrared spectrum of electromagnetic radiation; means for selecting an indoor environmental state when (a) the first reading of light within the visible spectrum of electromagnetic radiation is above a first threshold and (b) the second reading of light within the infrared spectrum of electromagnetic radiation is below a second threshold; and means for transitioning a Global Positioning System (GPS) sensor to a power savings mode based on the indoor environmental state being selected. For instance, such a technique may determine the GPS sensor is inside based on relatively low infrared readings and relatively high visible spectra readings, and responsively transition the GPS sensor into a more power efficient mode.

Abstract translation: 根据本文公开的实施例，提供了通过检测室内使用来节省GPS功率的系统，装置和方法。 例如，在一个实施例中，这种装置可以包括用于接收电磁辐射的可见光谱内的光的第一次读取的装置; 用于在电磁辐射的红外光谱内接收第二次读取光的装置; 当（a）电磁辐射的可见光谱内的光的第一次读取高于第一阈值时，以及（b）电磁辐射的红外光谱内的光的第二次读数低于第二阈值的装置，用于选择室内环境状态; 以及用于基于所选择的室内环境状态将全球定位系统（GPS）传感器转换到省电模式的装置。 例如，这种技术可以基于相对低的红外读数和相对高的可见光谱读数来确定GPS传感器在内部，并且将GPS传感器响应地转换成更有效的模式。

公开(公告)号：WO2013101251A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068287

申请日：2011-12-31

Applicant: INTEL CORPORATION ,  BRANDT, Jason ,  TYLER, Jonathan ,  ZURAWSKI, John ,  LASTOR, Dennis

Inventor： BRANDT, Jason ,  TYLER, Jonathan ,  ZURAWSKI, John ,  LASTOR, Dennis

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F11/30 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/805

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing Real Time Instruction Tracing compression of RET instructions For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets describing the instruction tracing; and means for compressing a multi-bit RET instruction (RETurn instruction) to a single bit RET instruction.

Abstract translation: 根据本文公开的实施例，提供了用于实现RET指令的实时指令跟踪压缩的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有用于发起指令跟踪的装置的集成电路 用于由跟踪的应用程序，模式或代码区域的指令，因为指令由集成电路执行; 用于产生描述所述指令跟踪的多个分组的装置; 以及用于将多位RET指令（RETurn指令）压缩到单个位RET指令的装置。

公开(公告)号：WO2013101246A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068281

申请日：2011-12-31

Applicant: INTEL CORPORATION ,  DATTA, Shamanna M. ,  PARTHASARATHY, Rajesh S. ,  NATU, Mahesh S. ,  BINNS, Frank ,  KUMAR, Mohan J.

Inventor： DATTA, Shamanna M. ,  PARTHASARATHY, Rajesh S. ,  NATU, Mahesh S. ,  BINNS, Frank ,  KUMAR, Mohan J.

IPC: G06F21/20 ,  G06F21/22 ,  G06F11/08

CPC classification number: G06F11/0754 ,  G06F12/1441 ,  G06F21/52

Abstract: A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.

Abstract translation: 描述了一种方法，其包括通过将系统管理程序代码的存储器访问指令的目标存储器地址再次比较来检测系统管理模式程序代码的存储器访问尝试通过存储器的受保护区域之外的程序代码来再次获得 定义保护区域的范围。 该方法还包括响应于检测而提高误差信号。

公开(公告)号：WO2017171890A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025780

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： MA, Hyungjin ,  LAL, Vasudev ,  JEONG, Seongtae ,  HOGGAN, Erik N.

IPC: G03F1/36 ,  G03F7/20

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm. For instance, in accordance with one embodiment, there are means described for creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences. Other related embodiments are disclosed.

Abstract translation: 根据所公开的实施例，提供了用于经由机器学习算法减少光学邻近校正（OPC）模型错误的方法，系统和设备。 例如，根据一个实施例，描述了用于通过光刻工艺形成掩模的装置; 使用所述掩模制造物理硅晶片，所述物理硅晶片具有由所述掩模限定的其中包含的多个特征; 使用用于创建掩模的光刻工艺的物理参数来创建掩模的半物理模型，所述半物理模型指定掩模的多个特征的轮廓; 捕获体现在物理硅晶片内的多个特征的扫描电子显微镜（SEM）图像; 量化（a）由半物理模型指定的掩模的多个特征的轮廓和（b）由SEM图像捕获的物理硅晶片内实施的多个特征之间的差异; 以及基于量化的差异移动由半物理模型指定的掩模的多个特征的轮廓。 披露了其他相关的实施例。