公开(公告)号：WO2019005107A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040286

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： CHANG, Je-Young ,  JHA, Chandra M. ,  DEVASENATHIPATHY, Shankar ,  EID, Feras ,  JOHNSON, John C.

IPC: H01L23/367

Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

公开(公告)号：WO2019005152A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040482

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： EID, Feras ,  GUTHIKONDA, Venkata Suresh R. ,  DEVASENATHIPATHY, Shankar ,  JHA, Chandra M. ,  CHANG, Je-Young ,  YAZZIE, Kyle ,  RAGHAVAN, Prasanna ,  MALATKAR, Pramod

IPC: H01L23/485 ,  H01L23/36 ,  H01L23/00 ,  H01L21/027

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

公开(公告)号：WO2017095385A1

公开(公告)日：2017-06-08

申请号：PCT/US2015/063046

申请日：2015-11-30

Applicant: INTEL CORPORATION

Inventor： JHA, Chandra M. ,  LI, Eric

IPC: H01L23/34 ,  H01L23/12

CPC classification number: H01L23/433 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/3737

Abstract: An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive materila and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.

Abstract translation: 描述了包括第一半导体管芯的设备。 第二半导体管芯堆叠在第一半导体管芯上。 第一半导体管芯具有比第二半导体管芯大的表面积，使得存在未被第二半导体管芯覆盖的第一半导体管芯的外围区域。 该设备包括在第二半导体管芯上方的导热材料。 该设备包括在导热材料与第二半导体管芯和第一半导体管芯的外围区域之间的复合模具。 该设备包括延伸穿过复合模具的导热结构，其将外围区域热耦合到导热材料。

公开(公告)号：WO2018063634A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/048846

申请日：2017-08-28

Applicant: INTEL CORPORATION

Inventor： CETEGEN, Edvin ,  KARHADE, Omkar G. ,  DHANE, Kedar ,  JHA, Chandra M.

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40

Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

Abstract translation: 热接口可以包括由第一TIM构成的有线网络和围绕有线网络的第二TIM。 散热器盖可以包括附接到散热器盖的内表面的有线网络。 IC封装可以包括放置在第一电子部件和第二电子部件上的散热器盖。 第一热界面可以形成在第一电子部件和散热器盖的内表面之间，并且第二热界面可以形成在第二电子部件和散热器盖的内表面之间。 第一热接口可以包括由第二TIM围绕的第一TIM的有线网络，而第二热接口可以包括第二TIM，而不具有第一TIM的有线网络。 其他实施例可以被描述和/或要求保护。

公开(公告)号：WO2017171889A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025779

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： MUTHUR SRINATH, Purushotham Kaushik ,  MALATKAR, Pramod ,  AGRAHARAM, Sairam ,  JHA, Chandra M. ,  CHOUDHURY, Arnab ,  RARAVIKAR, Nachiket R.

IPC: H01L23/12 ,  H01L23/48

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

Abstract translation: 根据所公开的实施例，提供了用于实现3D封装的热解决方案的方法，系统和设备。 例如，根据一个实施例，存在一种设备，其中具有：其中具有电迹线的衬底层; 与所述衬底层的电迹线电接合的第一层功能硅芯片，所述第一层功能硅芯片具有集成在其上的第一热衬垫; 位于所述第一层功能硅晶粒上方的第二层功能硅晶粒，所述第二层功能硅晶粒具有集成于其上的第二导热垫; 以及位于所述第一层功能硅管芯和所述第二层功能硅管芯之间的导电层，其中所述导电层用于：（i）将所述第二层功能硅管芯电连接到所述第一层功能硅管芯和（ii） 第一层功能硅的第一导热焊盘通过焊料与第二层功能硅芯片的第二导热焊盘相接合。 披露了其他相关的实施例。