公开(公告)号：WO2014105175A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/047706

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  SRINIVASA, Ganapati N. ,  WEISSMANN, Eliezer ,  KHANNA, Gaurav ,  NAIK, Mishali ,  FENGER, Russell J. ,  HENROID, Andrew D. ,  SUBBAREDDY, Dheeraj R. ,  KOUFATY, David A. ,  NARVAEZ, Paolo

Inventor： GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  SRINIVASA, Ganapati N. ,  WEISSMANN, Eliezer ,  KHANNA, Gaurav ,  NAIK, Mishali ,  FENGER, Russell J. ,  HENROID, Andrew D. ,  SUBBAREDDY, Dheeraj R. ,  KOUFATY, David A. ,  NARVAEZ, Paolo

IPC: G06F9/28 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/22

Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

Abstract translation: 一方面的处理器包括至少一个较低处理能力和较低功耗物理计算元件以及至少一个较高处理能力和较高功耗物理计算元件。 迁移性能优势评估逻辑是评估工作负载从至少一个较低处理能力计算元素迁移到至少一个较高处理能力计算元件的性能优点，并且基于以下步骤确定是否允许基于 评估性能好处。 可用的能源和热力预算评估逻辑是评估可用的能源和热预算，并确定如果迁移符合可用能源和热力预算，则允许迁移。 工作负载迁移逻辑是在迁移性能优势评估逻辑和可用的能源和热预算评估逻辑允许时执行迁移。

公开(公告)号：WO2014105058A1

公开(公告)日：2014-07-03

申请号：PCT/US2012/072135

申请日：2012-12-28

Applicant: INTEL CORPORATION ,  SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/06 ,  G06F1/32 ,  G06F9/46 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于并行执行软件线程的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

公开(公告)号：WO2013147801A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031249

申请日：2012-03-29

Applicant: INTEL CORPORATION ,  VARMA, Ankush ,  SISTLA, Krishnakanth ,  QUIROZ, Cesar ,  GARG, Vivek ,  ROWLAND, Martin ,  SODHI, Inder ,  BURNS, James

Inventor： VARMA, Ankush ,  SISTLA, Krishnakanth ,  QUIROZ, Cesar ,  GARG, Vivek ,  ROWLAND, Martin ,  SODHI, Inder ,  BURNS, James

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

Abstract translation: 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高的峰值性能。

公开(公告)号：WO2014105197A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/048352

申请日：2013-06-27

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  SODHI, Inder, M. ,  KHANNA, Gaurv ,  FENGER, Russel, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew D.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  SODHI, Inder, M. ,  KHANNA, Gaurv ,  FENGER, Russel, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew D.

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏小型物理处理器核心集。

公开(公告)号：WO2014105145A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046634

申请日：2013-06-19

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David A. ,  BRETT, Paul ,  HAHN, Scott D. ,  HERDRICH, Andrew J. ,  IYER, Ravishankar ,  CHITLUR, Nagabhushan ,  SODHI, Inder M. ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David A. ,  BRETT, Paul ,  HAHN, Scott D. ,  HERDRICH, Andrew J. ,  IYER, Ravishankar ,  CHITLUR, Nagabhushan ,  SODHI, Inder M. ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/28 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：WO2013101032A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067778

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  JAHAGIRDAR, Sanjeev, S. ,  GEORGE, Varghese ,  SODHI, Inder

Inventor： JAHAGIRDAR, Sanjeev, S. ,  GEORGE, Varghese ,  SODHI, Inder

IPC: G06F9/06 ,  G06F9/46 ,  G06F15/80

CPC classification number: G06F9/5083 ,  G06F9/30003 ,  G06F9/4856

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

Abstract translation: 一些实现提供了将线程从处理器的第一核心迁移到处理器的第二核心的技术和布置。 例如，一些实现可以标识被安排在处理器处执行的一个或多个线程。 处理器可以包括多个核，包括具有第一特征的第一核和第二核具有与第一特性不同的第二特性。 可以启动由第一核心执行一个或多个线程。 可以确定是否应用迁移策略。 响应于确定应用迁移策略，可以启动一个或多个线程从第一核到第二核的迁移。