公开(公告)号：WO2015084493A2

公开(公告)日：2015-06-11

申请号：PCT/US2014/060878

申请日：2014-10-16

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： PUSDESRIS, Joseph, Michael ,  KANG, Yiping ,  PELLEGRINI, Andrea ,  MUDGE, Trevor, Nigel ,  VANDERSLOOT, Benjamin, Allen

IPC: G06F9/30

CPC classification number: G06F12/023 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.

Abstract translation: 数据处理装置具有存储器重命名表，用于存储每个识别存储器中的位置的存储器地址和多个寄存器的映射寄存器之间的映射的存储器重命名条目。 映射的寄存器由寄存器编号标识。 响应于存储指令，存储指令的存储目标存储器地址被映射到存储目的地寄存器，因此将数据值存储到存储目的地寄存器而不是存储器。 在表中提供存储器重命名条目以识别存储目标存储器地址和存储目的地目标寄存器之间的映射。 响应于加载指令，如果存储器重命名表中存在针对加载目标存储器地址的命中，则可以从映射的寄存器而不是存储器读取加载的值。

公开(公告)号：WO2006115474A1

公开(公告)日：2006-11-02

申请号：PCT/US2005/013555

申请日：2005-04-21

Applicant: ARM LIMITED ,  UNIVERSTY OF MICHIGAN ,  BLAAUW, David, Theodore ,  BULL, David, Michael ,  DAS, Shidhartha

Inventor： BLAAUW, David, Theodore ,  BULL, David, Michael ,  DAS, Shidhartha

IPC: G06F11/14

CPC classification number: G06F11/1407

Abstract: An integrated circuit comprises an error detection circuit 3230-1 to 3230-4 operable to detect a transition in the signal value in a predetermined time window, which is indicative of an error in operation of the integrated circuit. The integrated circuit also comprises a storage unit 3296 operable to store a recoverable state of the data processing apparatus comprising at least a subset of architectural state variables corresponding to a programmer's model of the integrated circuit. An error recovery circuit 3250, 3260,3210 is provided as part of the integrated circuit and this serves to enable the integrated circuit to recover from detected errors in operation using the stored recoverable state from the storage unit 3296. An operational parameter controller 3242 of the integrated circuit adjusts the operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature in dependence upon one or more characteristics of detected errors in operation so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Abstract translation: 集成电路包括错误检测电路3230-1至3230-4，其可操作以检测指示集成电路的操作中的错误的预定时间窗中的信号值中的转变。 集成电路还包括存储单元3296，其可操作以存储数据处理装置的可恢复状态，该可恢复状态包括与集成电路的编程器模型对应的架构状态变量的至少一个子集。 作为集成电路的一部分提供了错误恢复电路3250,3260,3210，并且这用于使得集成电路能够使用来自存储单元3296的存储的可恢复状态的操作中的检测到的错误恢复。 集成电路根据操作中检测到​​的错误的一个或多个特性调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度，以保持有限的非零误码率 以提高整体性能的方式。

公开(公告)号：WO2013130090A1

公开(公告)日：2013-09-06

申请号：PCT/US2012/027359

申请日：2012-03-02

Applicant: ARM LIMITED ,  FLANDERS, William, Henry ,  PRASADH, Ramamoorthy, Guru ,  TUMMALA, Ashok, Kumar ,  JALAL, Jamshed ,  MANNAVA, Phanindra, Kumar

Inventor： FLANDERS, William, Henry ,  PRASADH, Ramamoorthy, Guru ,  TUMMALA, Ashok, Kumar ,  JALAL, Jamshed ,  MANNAVA, Phanindra, Kumar

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F2212/60

Abstract: A data processing apparatus (2) comprises a first protocol domain A configured to operate under a write progress protocol and a second protocol domain B configured to operate under a snoop progress protocol. A deadlock condition is detected if a write target address for a pending write request issued from the first domain A to the second domain B is the same as a snoop target address or a pending snoop request issued from the second domain B to the first domain A. When the deadlock condition is detected, a bridge (4) between the domains may issue an early response to a selected one of the deadlocked write and snoop requests without waiting for the selected request serviced. The early response indicates to the domain that issued the selected request that the selected request has been serviced, enabling the other request to be serviced by the issuing domain.

Abstract translation: 数据处理装置（2）包括被配置为在写入进程协议下操作的第一协议域A和被配置为在侦听进程协议下操作的第二协议域B. 如果从第一域A发送到第二域B的待决写入请求的写入目标地址与从第二域B向第一域A发出的窥探目标地址或未决侦听请求相同，则检测到死锁条件 当检测到死锁状况时，域之间的桥（4）可以对所选择的一个死锁写和窥探请求发出早期响应，而不等待所服务的所选择的请求。 早期响应向发出所选择的请求的域指示所选择的请求已经被服务，使得发出域能够服务其他请求。

公开(公告)号：WO2009067219A8

公开(公告)日：2009-05-28

申请号：PCT/US2008/012935

申请日：2008-11-20

Applicant: ARM LIMITED ,  THE REGENTS OF THE UNIVERSITY OF MICHIGAN ,  BLAKE, Geoffrey ,  MUDGE, Trevor, Nigel ,  BILES, Stuart, David ,  CHONG, Nathan, Yong Seng ,  OZER, Emre ,  DRESLINSKI, Ronald, George

Inventor： BLAKE, Geoffrey ,  MUDGE, Trevor, Nigel ,  BILES, Stuart, David ,  CHONG, Nathan, Yong Seng ,  OZER, Emre ,  DRESLINSKI, Ronald, George

IPC: G06F9/46

Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

公开(公告)号：WO2015080806A1

公开(公告)日：2015-06-04

申请号：PCT/US2014/060393

申请日：2014-10-14

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： PADMANABHA, Shruti ,  LUKEFAHR, Andrew ,  DAS, Reetuparna ,  MAHLKE, Scott

IPC: G06F9/38

CPC classification number: G06F9/30058 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/3836 ,  Y02D10/122 ,  Y02D10/24

Abstract: An apparatus 2 for processing data includes first execution circuitry 4, such as an out-of-order processor, and second execution circuitry 6, such as an in-order processor. The first execution circuitry 4 is of higher performance but uses more energy than the second execution circuitry 6. Control circuitry 24 switches between the first execution circuitry 4 being active and the second execution circuitry 6 being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.

Abstract translation: 用于处理数据的装置2包括诸如无序处理器的第一执行电路4和诸如按顺序处理器的第二执行电路6。 第一执行电路4具有更高的性能，但是比第二执行电路6使用更多的能量。控制电路24在有效的第一执行电路4和有效的第二执行电路6之间切换。 控制电路包括预测电路，其被配置为根据最近执行的程序指令序列预测要执行的下一个程序指令序列的预测身份，然后根据该预测的身份来预测相应的预测执行目标 是否应该由第一执行电路或第二执行电路执行下一个程序指令序列。

公开(公告)号：WO2014084817A3

公开(公告)日：2014-06-05

申请号：PCT/US2012/066745

申请日：2012-11-28

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： SAMPSON, Richard ,  WENISCH, Thomas, Friedrich

IPC: G06F9/46

Abstract: A data processing system is provided for performing processing operations upon an ordered stream of input data values to form an ordered stream of output data values. A select circuit (18) includes select interval generation circuitry (34) which determines a number (interval number) of input data values between each data value to be selected for output from among the ordered stream of input data values. This interval number varies with position within the ordered stream of input data values. The select circuit (18) can thus perform selection of input data values in accordance with an interval number which may be varied, for example, in accordance with a linear piecewise approximation of an desired curve or, in other embodiments, in a piecewise quadratic variation approximating a desired curve. The processing techniques may be used, for example, in beam forming application, such as 3D beam forming of ultrasonic images.

公开(公告)号：WO2012082092A1

公开(公告)日：2012-06-21

申请号：PCT/US2010/059996

申请日：2010-12-13

Applicant: ARM LIMITED ,  MCLAURIN, Teresa, Louise

Inventor： MCLAURIN, Teresa, Louise

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is formed of a plurality of circuit dies 22, 24 having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks.

Abstract translation: 集成电路由具有通过硅通孔（TSV）的多个电路管芯22,24形成。 通孔硅通孔的布置图案在电路管芯之间不同。 芯片间路由层被提供在电路管芯之一的衬底的表面或电路管芯之一的处理电路层的外表面中。 管芯间布线层桥接了通孔和不同电路管芯的连接点之间的间隙。 芯片间布线层可以由金属轨道形成。