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    DETERMINING DESIGN COORDINATES FOR WAFER DEFECTS
    1.
    发明申请
    DETERMINING DESIGN COORDINATES FOR WAFER DEFECTS 审中-公开
    确定晶圆缺陷的设计坐标

    公开(公告)号：WO2013040063A2

    公开(公告)日：2013-03-21

    申请号：PCT/US2012/054904

    申请日：2012-09-12

    Applicant: KLA-TENCOR CORPORATION ,  CHANG, Ellis ,  VAN RIET, Michael ,  PARK, Allen ,  ZAFAR, Khurram ,  BHATTACHARYYA, Santosh

    Inventor： CHANG, Ellis ,  VAN RIET, Michael ,  PARK, Allen ,  ZAFAR, Khurram ,  BHATTACHARYYA, Santosh

    IPC: H01L21/66

    CPC classification number: G06T7/001 ,  G06T7/74 ,  G06T2207/30148

    Abstract: Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

    Abstract translation: 提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。 一种方法包括：通过检查工具将晶片的设计与晶片上的多个条带中检测到的缺陷的缺陷评论工具图像对齐，基于对齐的结果确定设计坐标中每个缺陷的位置，分别确定缺陷 基于检测到每个缺陷的条带（条带校正因子），每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置，确定多个条带中的每个条带的位置偏移;以及 通过对这些缺陷应用合适的刈幅校正因子来确定检查工具在多个刈幅中检测到的其他缺陷的设计坐标。

    METHODS AND SYSTEMS FOR DETERMINING A DEFECT CRITICALITY INDEX FOR DEFECTS ON WAFERS
    2.
    发明申请
    METHODS AND SYSTEMS FOR DETERMINING A DEFECT CRITICALITY INDEX FOR DEFECTS ON WAFERS 审中-公开
    用于确定缺陷关键指标的方法和系统

    公开(公告)号：WO2009129105A3

    公开(公告)日：2010-01-21

    申请号：PCT/US2009039936

    申请日：2009-04-08

    Applicant: KLA ENCOR CORP ,  CHEN CHIEN-HUEI ADAM ,  XIONG YAN ,  ZHANG JIANXIN ,  CHANG ELLIS ,  FANG TSUNG-PAO

    Inventor： CHEN CHIEN-HUEI ADAM ,  XIONG YAN ,  ZHANG JIANXIN ,  CHANG ELLIS ,  FANG TSUNG-PAO

    IPC: H01L21/66

    CPC classification number: G01R31/318511 ,  G06T7/0004 ,  G06T2207/30148

    Abstract: Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.

    Abstract translation: 提供了用于确定晶片缺陷的缺陷关键指数（DCI）的各种方法和系统。 一种计算机实现的方法包括：基于由检查系统报告的缺陷的位置以及由检测系统报告的缺陷的大小，通过检查系统确定围绕在晶片上检测到的缺陷的晶片的部分设计的关键区域信息 检查系统。 该方法还包括基于关键区域信息，缺陷相对于关键区域信息的位置以及报告的缺陷大小来确定缺陷的DCI。

    METHODS AND SYSTEMS FOR DETERMINING A DEFECT CRITICALITY INDEX FOR DEFECTS ON WAFERS
    3.
    发明申请
    METHODS AND SYSTEMS FOR DETERMINING A DEFECT CRITICALITY INDEX FOR DEFECTS ON WAFERS 审中-公开
    用于确定缺陷关键指标的方法和系统

    公开(公告)号：WO2009129105A2

    公开(公告)日：2009-10-22

    申请号：PCT/US2009/039936

    申请日：2009-04-08

    Applicant: KLA-ENCOR CORPORATION ,  CHEN, Chien-Huei (Adam) ,  XIONG, Yan ,  ZHANG, Jianxin ,  CHANG, Ellis ,  FANG, Tsung-Pao

    Inventor： CHEN, Chien-Huei (Adam) ,  XIONG, Yan ,  ZHANG, Jianxin ,  CHANG, Ellis ,  FANG, Tsung-Pao

    IPC: H01L21/66

    CPC classification number: G01R31/318511 ,  G06T7/0004 ,  G06T2207/30148

    Abstract: Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.

    Abstract translation: 提供了用于确定晶片缺陷的缺陷关键指数（DCI）的各种方法和系统。 一种计算机实现的方法包括：基于由检查系统报告的缺陷的位置以及由检测系统报告的缺陷的大小，通过检查系统确定围绕在晶片上检测到的缺陷的晶片的部分设计的关键区域信息 检查系统。 该方法还包括基于关键区域信息，缺陷相对于关键区域信息的位置以及报告的缺陷大小来确定缺陷的DCI。

    DETERMINING DESIGN COORDINATES FOR WAFER DEFECTS
    5.
    发明申请
    DETERMINING DESIGN COORDINATES FOR WAFER DEFECTS 审中-公开
    确定缺陷的设计坐标

    公开(公告)号：WO2013040063A3

    公开(公告)日：2013-06-27

    申请号：PCT/US2012054904

    申请日：2012-09-12

    Applicant: KLA TENCOR CORP ,  CHANG ELLIS ,  VAN RIET MICHAEL ,  PARK ALLEN ,  ZAFAR KHURRAM ,  BHATTACHARYYA SANTOSH

    Inventor： CHANG ELLIS ,  VAN RIET MICHAEL ,  PARK ALLEN ,  ZAFAR KHURRAM ,  BHATTACHARYYA SANTOSH

    IPC: H01L21/66

    CPC classification number: G06T7/001 ,  G06T7/74 ,  G06T2207/30148

    Abstract: Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

    Abstract translation: 提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。 一种方法包括对准晶片的设计以通过检查工具对晶片上的多个条带中检测到的缺陷来检查工具图像，基于对准的结果确定每个缺陷在设计坐标中的位置，分别确定缺陷 基于检测到每个缺陷的条带（条纹校正因子），每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置，针对每个多个条带的位置偏移，以及 通过对这些缺陷应用适当的条纹校正因子来确定检测工具在多个条中检测到的其他缺陷的设计坐标。

    SCANNER PERFORMANCE COMPARISON AND MATCHING USING DESIGN AND DEFECT DATA
    6.
    发明申请
    SCANNER PERFORMANCE COMPARISON AND MATCHING USING DESIGN AND DEFECT DATA 审中-公开
    扫描仪性能比较和匹配使用设计和缺陷数据

    公开(公告)号：WO2011008688A3

    公开(公告)日：2011-05-05

    申请号：PCT/US2010041697

    申请日：2010-07-12

    Applicant: KLA TENCOR CORP ,  PARK ALLEN ,  CHANG ELLIS ,  AOKI MASAMI ,  YOUNG CHRIS CHIH-CHIEN ,  PLIHAL MARTIN ,  VAN RIET MICHAEL JOHN

    Inventor： PARK ALLEN ,  CHANG ELLIS ,  AOKI MASAMI ,  YOUNG CHRIS CHIH-CHIEN ,  PLIHAL MARTIN ,  VAN RIET MICHAEL JOHN

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70641 ,  G03F7/7065

    Abstract: A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a "no match". Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.

    Abstract translation: 描述使用设计和缺陷数据匹配多个扫描仪的系统和方法。 使用金色工具处理金色晶圆。 使用第二工具处理第二晶片。 两种工具都提供对焦/曝光调制。 可以比较两个晶片的关键结构的晶片级空间特征，以评估扫描仪的行为。 关键结构可以通过在具有相似图案的金色晶片上合并缺陷来识别。 在一个实施例中，签名必须在一定百分比内匹配，或者第二工具被表征为“不匹配”。 可以以类似的方式比较网状物，其中分别使用金色掩模版和第二掩模版来处理金色和第二晶片。

    COMPUTER-IMPLEMENTED METHODS, CARRIER MEDIA, AND SYSTEMS FOR GENERATING A METROLOGY SAMPLING PLAN
    7.
    发明申请
    COMPUTER-IMPLEMENTED METHODS, CARRIER MEDIA, AND SYSTEMS FOR GENERATING A METROLOGY SAMPLING PLAN 审中-公开
    计算机实现方法，载体介质和用于生成计量采样计划的系统

    公开(公告)号：WO2009023571A1

    公开(公告)日：2009-02-19

    申请号：PCT/US2008/072636

    申请日：2008-08-08

    Applicant: KLA-TENCOR CORPORATION ,  PARK, Allen ,  CHANG, Ellis

    Inventor： PARK, Allen ,  CHANG, Ellis

    IPC: H01L21/66

    CPC classification number: G05B23/0221

    Abstract: Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.

    Abstract translation: 提供了各种计算机实现的方法，载体介质和用于生成计量抽样计划的系统。 用于生成计量取样计划的一种计算机实现的方法包括从包含各个缺陷的缺陷群体的一个或多个属性识别具有一个或多个属性异常的一个或多个单个缺陷。 缺陷的群体位于晶片上的预定图案中。 该方法还包括基于识别步骤的结果生成计量取样计划，使得在测量期间采样一个或多个所识别的单个缺陷所在的晶片上的一个或多个区域。

    METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA
    10.
    发明申请
    METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA 审中-公开
    与检验数据组合使用设计数据的方法和系统

    公开(公告)号：WO2007120279A2

    公开(公告)日：2007-10-25

    申请号：PCT/US2006/061112

    申请日：2006-11-20

    Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  ZAFAR, Khurram ,  KEKARE, Sagar ,  CHANG, Ellis ,  PARK, Allen ,  ROSE, Peter

    Inventor： ZAFAR, Khurram ,  KEKARE, Sagar ,  CHANG, Ellis ,  PARK, Allen ,  ROSE, Peter

    IPC: G06F17/50

    CPC classification number: G01N21/9501 ,  G01N2021/8854 ,  G01R31/31718 ,  G06T7/001 ,  G06T2207/30148 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

    Abstract translation: 提供了与检测数据结合使用设计数据的各种方法和系统。 用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。 该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。 此外，该方法包括将组中的缺陷合并，使得接近每个组中的缺陷位置的设计数据的部分至少相似。 该方法还包括将合并步骤的结果存储在存储介质中。

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