公开(公告)号：WO2014013288A1

公开(公告)日：2014-01-23

申请号：PCT/IB2012/001608

申请日：2012-07-19

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  PUJOL, Alexandre ,  GIVELIN, Philippe ,  MANSRI, Mohammed

Inventor： PUJOL, Alexandre ,  GIVELIN, Philippe ,  MANSRI, Mohammed

IPC: G05F1/10 ,  G05F1/565

CPC classification number: G05F1/625 ,  G05F1/565 ,  G05F1/573 ,  G05F1/575 ,  G05F1/59 ,  H02M3/158

Abstract: The present invention pertains to a linear power regulator device (10), comprising an internal pass device (32), a driver device (20) having a driver output (27) arranged to drive the internal pass device (32) via the driver output (27), wherein the linear power regulator device (10) comprises an external connection (34) connectable or connected to an external pass device (50); and wherein the driver device (20) is arranged to drive an external pass device (50) via the driver output (33) and the external connection (34). The invention also pertains to a corresponding electronic device.

Abstract translation: 本发明涉及一种线性功率调节器装置（10），其包括内部通过装置（32），具有驱动器输出（27）的驱动器装置（20），驱动器输出（27）被布置成通过驱动器输出驱动内部通过装置（32） （27），其中所述线性功率调节器装置（10）包括可连接或连接到外部通过装置（50）的外部连接（34）。 并且其中所述驱动器装置（20）被布置成经由所述驱动器输出（33）和所述外部连接（34）驱动外部通过装置（50）。 本发明还涉及相应的电子设备。

公开(公告)号：WO2012164332A1

公开(公告)日：2012-12-06

申请号：PCT/IB2011/001591

申请日：2011-05-27

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  GIVELIN, Philippe ,  BESSE, Patrice ,  HUYNH, Estelle

Inventor： GIVELIN, Philippe ,  BESSE, Patrice ,  HUYNH, Estelle

IPC: G01R31/28 ,  G01R31/04 ,  H03K17/06

CPC classification number: H02H1/0007 ,  G01R31/025 ,  G01R31/2853 ,  G01R31/2884

Abstract: A reference voltage loss monitoring circuit comprises a first reference node (51) and a second reference node(52). The reference nodes are arranged to be connected to a voltage reference (Vref). A first connection device (1) is arranged to connect the first reference node to the second reference node, and comprises a first diode (11) arranged to allow a current flowing from the first reference node to the reference ground node and not conversely. The first diode comprises a first main transistor (12) connected to operate as a diode. A second connection device (2) is arranged to connect the second reference node to the first reference node, and comprises a second diode (21) arranged to allow a current flowing from the second reference node to first reference node and not conversely. The second diode comprises a second main transistor (22) connected to operate as a diode. Each of the first and second connection devices further comprises a secondary transistor (14, 24) mirrored with the main transistor of the first and second connection devices respectively. The secondary transistor comprises an output arranged to be coupled to a diagnostic circuit (90), for delivering to the diagnostic circuit a signal indicative of a loss of voltage reference on a respective reference node.

Abstract translation: 参考电压损失监测电路包括第一参考节点（51）和第二参考节点（52）。 参考节点被布置成连接到电压参考（Vref）。 第一连接装置（1）被布置成将第一参考节点连接到第二参考节点，并且包括布置成允许电流从第一参考节点流向参考接地节点的第一二极管（11），而不是相反。 第一二极管包括连接以作为二极管工作的第一主晶体管（12）。 第二连接装置（2）被布置成将第二参考节点连接到第一参考节点，并且包括布置成允许电流从第二参考节点流向第一参考节点而不是相反的第二二极管（21）。 第二二极管包括连接以作为二极管工作的第二主晶体管（22）。 第一和第二连接装置中的每一个还包括分别与第一和第二连接装置的主晶体管镜像的次级晶体管（14,24）。 次级晶体管包括布置成耦合到诊断电路（90）的输出，用于将指示相应参考节点上的电压基准损耗的信号传送到诊断电路。

公开(公告)号：WO2013160713A1

公开(公告)日：2013-10-31

申请号：PCT/IB2012/001066

申请日：2012-04-26

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BESSE, Patrice ,  BERNON-ENJALBERT, Valérie ,  GIVELIN, Philippe

Inventor： BESSE, Patrice ,  BERNON-ENJALBERT, Valérie ,  GIVELIN, Philippe

IPC: H03K17/08 ,  H01L27/04

CPC classification number: G01R31/002 ,  H01L27/0251 ,  H03K17/08122 ,  H03K17/0822

Abstract: An electronic device (10) for generating an error signal in response to an electrostatic discharge perturbation is described. The device (10) may comprise: a detection unit (34; 36; 38) for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock (26) for generating a clock signal having a clock period; and a protection unit (28) for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.

Abstract translation: 描述了用于响应于静电放电扰动产生误差信号的电子设备（10）。 所述装置（10）可以包括：检测单元（34; 36; 38），用于响应于所述静电放电扰动产生检测信号，所述检测信号在时间上与所述静电放电扰动相关; 用于产生具有时钟周期的时钟信号的时钟（26）; 以及保护单元（28），用于仅当所述检测信号的持续时间超过所述时钟周期的预定倍数时，响应于所述检测信号产生误差信号。 还公开了一种响应于静电放电扰动产生用于保护电子电路的误差信号的方法。

公开(公告)号：WO2013061110A1

公开(公告)日：2013-05-02

申请号：PCT/IB2011/003298

申请日：2011-10-27

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  GIVELIN, Philippe ,  BERNON-ENJALBERT, Valérie ,  FOUNAUD, Guillaume

Inventor： GIVELIN, Philippe ,  BERNON-ENJALBERT, Valérie ,  FOUNAUD, Guillaume

IPC: B60R16/02 ,  G06F1/26 ,  H02J1/14 ,  H02J7/14 ,  H02J9/06 ,  B60R16/03

CPC classification number: H02J9/061 ,  B60R21/0173 ,  B60T8/885 ,  B60T2270/414 ,  Y10T307/615

Abstract: A power safety circuit (30) comprises a power sense terminal (32); an output terminal (34); an output driver unit (36) connected to the output terminal; an input terminal (38) connectable to receive a first power from a power source (40) and arranged to supply the first power to the output driver unit; and a power detection unit (42) arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device (50) comprises at least one power safety circuit (30). A safety critical system (60) comprises at least one integrated circuit device (50) with at least one power safety circuit (30).

Abstract translation: 电力安全电路（30）包括功率检测端子（32）; 输出端子（34）; 输出驱动器单元（36），连接到所述输出端子; 输入端子（38），其可连接以从电源（40）接收第一功率并被布置成将第一功率提供给所述输出驱动器单元; 以及功率检测单元，被配置为检测所述输入端子的状态并向所述功率检测端子提供功率检测信号; 其中所述功率检测端子被布置成当所述功率检测信号指示所述第一功率的电平低于用于驱动所述输出端子的最小电平时，向所述输出驱动器单元提供第二功率。 集成电路装置（50）包括至少一个电力安全电路（30）。 安全关键系统（60）包括具有至少一个电力安全电路（30）的至少一个集成电路装置（50）。

公开(公告)号：WO2014006442A1

公开(公告)日：2014-01-09

申请号：PCT/IB2012/002539

申请日：2012-07-02

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BERNON-ENJALBERT, Valérie ,  FOUNAUD, Guillaume ,  GAO, Yuan ,  GIVELIN, Philippe

Inventor： BERNON-ENJALBERT, Valérie ,  FOUNAUD, Guillaume ,  GAO, Yuan ,  GIVELIN, Philippe

IPC: H01L27/00 ,  B60R16/02

CPC classification number: G01R31/2851 ,  G01R31/3177 ,  G01R31/3187 ,  G06F17/5045 ,  G06F2217/70 ,  H01L21/22 ,  H01L21/76224 ,  H01L27/0207 ,  H01L29/0642 ,  H01L29/0649

Abstract: An integrated circuit device (100) comprises a first integrated circuit (101) and a second integrated circuit (102) wherein the first and second integrated circuits (101, 102) are comprised on a single semiconductor die (100). The second integrated circuit (102) is a safety circuit (102) arranged to monitor the operation of the first integrated circuit (101), report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit (101) may be a power management module for a safety critical system. An isolation barrier in the form of a trench (107) is formed between the two integrated circuits (101, 102) so that the safety circuit (102) is protected from any high voltage or thermal stresses arising in the first integrated circuit (101). The device (100) has particular application to automotive safety-critical systems such as electric power steering systems.

Abstract translation: 集成电路装置（100）包括第一集成电路（101）和第二集成电路（102），其中第一和第二集成电路（101,102）包括在单个半导体管芯（100）上。 第二集成电路（102）是用于监视第一集成电路（101）的操作的安全电路（102），报告任何检测到的故障，并且如果检测到故障则将设备驱动到故障安全状态。 第一集成电路（101）可以是用于安全关键系统的电源管理模块。 在两个集成电路（101,102）之间形成有沟槽（107）形式的隔离屏障，使得安全电路（102）不受第一集成电路（101）中产生的任何高压或热应力的影响， 。 该设备（100）具有特别适用于诸如电动助力转向系统的汽车安全关键系统。

公开(公告)号：WO2013179078A1

公开(公告)日：2013-12-05

申请号：PCT/IB2012/001208

申请日：2012-05-30

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BESSE, Patrice ,  ABOUDA, Kamel ,  BERNON-ENJALBERT, Valérie ,  GIVELIN, Philippe

Inventor： BESSE, Patrice ,  ABOUDA, Kamel ,  BERNON-ENJALBERT, Valérie ,  GIVELIN, Philippe

IPC: H01L23/60 ,  H01L27/04

CPC classification number: H01L23/60 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0262 ,  H01L27/04 ,  H01L29/74 ,  H01L29/7436 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/13034 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device (1) comprising a package (2) and a semiconductor device (3) is described. The semiconductor device (3) comprises a first and a second GND-pad (31, 32) bonded to one or more GND-pins (11, 12) with a first and a second bond wire (B1, B2) respectively, a first functional pad (33) bonded to a first functional pin (13) with a third bond wire (B3), a semiconductor layer (10) of a P-type conductivity, a first semiconductor component (34) and a second semiconductor component (37). The first semiconductor component (34) is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN- junction (J1). The second semiconductor component (37) comprises a second N-type region (N2) of a terminal of the second semiconductor component (37) associated with the first functional pad. The first GND-pad (31) is in contact with a second P-type region. The second GND-pad (32) is in contact with a third N-type region. At least part (P2a) of the second P-type region is arranged in between the first semiconductor component (34) and the second semiconductor component (37), and at least part of the third N-type region is arranged in between the at least part of the first P-type region (P1) and the second semiconductor component (37).

Abstract translation: 描述了包括封装（2）和半导体器件（3）的封装半导体器件（1）。 半导体器件（3）包括分别与第一和第二接合线（B1，B2）接合到一个或多个GND-引脚（11,12）的第一和第二GND-焊盘（31,32），第一 通过第三接合线（B3）与第一功能引脚（13）接合的功能焊盘（33），P型导电体的半导体层（10），第一半导体部件（34）和第二半导体部件（37） ）。 第一半导体部件（34）被布置成当瞬态电流施加到第一功能引脚时，将至少部分瞬态电流从第一P区域转移到第一GND焊盘至第一GND焊盘 至少第一PN结（J1）。 第二半导体部件（37）包括与第一功能焊盘相关联的第二半导体部件（37）的端子的第二N型区域（N2）。 第一GND焊盘（31）与第二P型区域接触。 第二GND焊盘（32）与第三N型区域接触。 第二P型区域的至少一部分（P2a）配置在第一半导体部件（34）和第二半导体部件（37）之间，第三N型区域的至少一部分配置在 第一P型区域（P1）和第二半导体部件（37）的至少一部分。

公开(公告)号：WO2013108065A1

公开(公告)日：2013-07-25

申请号：PCT/IB2012/000247

申请日：2012-01-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  BESSE, Patrice ,  GIVELIN, Philippe ,  ROLLAND, Eric

Inventor： BESSE, Patrice ,  GIVELIN, Philippe ,  ROLLAND, Eric

IPC: H01L27/04

CPC classification number: H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0647 ,  H01L29/7412 ,  H01L29/7428

Abstract: An integrated circuit (IC) device comprising at least one electrostatic discharge (ESD) protection network for a high voltage application. The at least one ESD protection network comprises a common diode structure operably coupled between at least one external contact of the IC device for which ESD protection is to be provided and a substrate of the IC device such that the common diode structure is forward biased towards the at least one external contact, at least one Darlington transistor structure operably coupled between the at least one external contact of the IC device for which ESD protection is to be provided and the substrate of the IC device, and the at least one Darlington transistor structure comprising: an emitter node operably coupled to the at least one external contact of the IC device; a collector node operably coupled to the substrate of the IC device; and a base node operably coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises at least one isolation diode structure operably coupled between the emitter node and the base node of the at least one Darlington transistor structure such that the at least one isolation diode structure is forward biased towards the base node.

Abstract translation: 一种集成电路（IC）装置，包括用于高电压应用的至少一个静电放电（ESD）保护网络。 所述至少一个ESD保护网络包括可操作地耦合在将要提供ESD保护的IC器件的至少一个外部触点与IC器件的衬底之间的公共二极管结构，使得公共二极管结构向前偏置 至少一个外部接触件，至少一个达林顿晶体管结构，其可操作地耦合在将要提供ESD保护的IC器件的至少一个外部触点与IC器件的衬底之间，以及至少一个达林顿晶体管结构， ：可操作地耦合到IC器件的至少一个外部触点的发射器节点; 可操作地耦合到IC器件的衬底的收集器节点; 以及可操作地耦合在达林顿晶体管结构的发射极节点和公共二极管结构之间的基极节点。 至少一个ESD保护网络还包括可操作地耦合在至少一个达林顿晶体管结构的发射极节点和基极节点之间的至少一个隔离二极管结构，使得至少一个隔离二极管结构朝向基极节点正向偏置。