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    ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS
    5.
    发明申请
    ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS 审中-公开
    基于DIPYRIDYL的电位器在微电子中电沉积铜

    公开(公告)号：WO2010062822A3

    公开(公告)日：2011-08-11

    申请号：PCT/US2009065053

    申请日：2009-11-19

    Applicant: ENTHONE ,  PANECCASIO VINCENT ,  LIN XUAN ,  HURTUBISE RICHARD ,  CHEN QINGYUN

    Inventor： PANECCASIO VINCENT ,  LIN XUAN ,  HURTUBISE RICHARD ,  CHEN QINGYUN

    IPC: C25D3/38 ,  C25D7/12 ,  H01L21/288

    CPC classification number: H01L21/76879 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

    Abstract translation: 一种用于金属化半导体集成电路器件衬底中的通孔特征的方法，其中所述半导体集成电路器件衬底包括前表面，后表面和所述通孔特征，并且其中所述通孔特征包括在所述衬底的前表面中的开口 ，从基板的前表面向内延伸的侧壁和底部。 该方法包括使半导体集成电路器件衬底与包含（a）铜离子源和（b）整平剂化合物的电解铜沉积化学物质接触，其中矫光剂化合物是二吡啶基化合物和烷基化剂的反应产物; 并向电解沉积化学物质提供电流以将铜金属沉积到通孔特征的底部和侧壁上，从而产生铜填充的通孔特征。

    COPPER ELECTRODEPOSITION IN MICROELECTRONICS
    9.
    发明申请
    COPPER ELECTRODEPOSITION IN MICROELECTRONICS 审中-公开
    铜电极在微电子学中的应用

    公开(公告)号：WO2006053242A3

    公开(公告)日：2006-06-29

    申请号：PCT/US2005040996

    申请日：2005-11-14

    Applicant: ENTHONE ,  PANECCASIO VINCENT ,  LIN XUAN ,  FIGURA PAUL ,  HURTUBISE RICHARD

    Inventor： PANECCASIO VINCENT ,  LIN XUAN ,  FIGURA PAUL ,  HURTUBISE RICHARD

    IPC: H01L21/31

    CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D7/12 ,  C25D7/123 ,  H01L21/76877

    Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.

    Abstract translation: 一种用于在具有亚微米尺寸互连特征的半导体集成电路基板上电解电镀Cu的电解电镀方法和组合物。 该组合物包含Cu离子源和包含聚醚基团的抑制化合物。 该方法包括以超填充速度的快速自下而上沉积来超填充，通过其从特征的底部到特征的顶部开口的垂直方向上的Cu沉积基本上大于侧壁上的Cu沉积。

    COPPER FILLING OF THROUGH SILICON VIAS
    10.
    发明申请
    COPPER FILLING OF THROUGH SILICON VIAS 审中-公开
    铜填充硅橡胶

    公开(公告)号：WO2011149965A3

    公开(公告)日：2012-04-19

    申请号：PCT/US2011037777

    申请日：2011-05-24

    Applicant: ENTHONE ,  RICHARDSON THOMAS B ,  SHAO WENBO ,  LIN XUAN ,  WANG CAI ,  PANECCASIO VINCENT JR ,  ABYS JOSEPH A ,  ZHANG YUN ,  HURTUBISE RICHARD ,  WANG CHEN

    Inventor： RICHARDSON THOMAS B ,  SHAO WENBO ,  LIN XUAN ,  WANG CAI ,  PANECCASIO VINCENT JR ,  ABYS JOSEPH A ,  ZHANG YUN ,  HURTUBISE RICHARD ,  WANG CHEN

    IPC: C25D3/38 ,  C25D5/02 ,  C25D7/12 ,  H01L21/768

    CPC classification number: C25D3/38 ,  C25D5/02 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76898

    Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature. The deposition composition comprises (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) an organic disulfide compound; (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof; and (d) chloride ions.

    Abstract translation: 一种用于在半导体集成电路器件衬底中金属化穿硅通孔特征的方法。 该方法包括将半导体集成电路器件衬底浸入电解铜沉积组合物中，其中通孔硅通孔特征具有介于1微米至100微米之间的入口尺寸，20微米至750微米的深度尺寸，以及大于 约2：1; 向电解沉积组合物供给电流以将铜金属沉积到底部和侧壁上以进行自底向上填充，由此产生铜填充的通孔特征。 沉积组合物包括（a）铜离子源; （b）选自无机酸，有机磺酸及其混合物的酸; （c）有机二硫化物; （d）选自苄基氯和羟乙基聚亚丙基亚胺的反应产物，季铵化吡啶基化合物及其组合的化合物; 和（d）氯离子。

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