ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS
    4.
    发明申请
    ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS 审中-公开
    基于DIPYRIDYL的电位器在微电子中电沉积铜

    公开(公告)号:WO2010062822A3

    公开(公告)日:2011-08-11

    申请号:PCT/US2009065053

    申请日:2009-11-19

    Abstract: A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

    Abstract translation: 一种用于金属化半导体集成电路器件衬底中的通孔特征的方法,其中所述半导体集成电路器件衬底包括前表面,后表面和所述通孔特征,并且其中所述通孔特征包括在所述衬底的前表面中的开口 ,从基板的前表面向内延伸的侧壁和底部。 该方法包括使半导体集成电路器件衬底与包含(a)铜离子源和(b)整平剂化合物的电解铜沉积化学物质接触,其中矫光剂化合物是二吡啶基化合物和烷基化剂的反应产物; 并向电解沉积化学物质提供电流以将铜金属沉积到通孔特征的底部和侧壁上,从而产生铜填充的通孔特征。

    ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS
    7.
    发明申请
    ELECTRODEPOSITION OF COPPER IN MICROELECTRONICS WITH DIPYRIDYL-BASED LEVELERS 审中-公开
    用DIPYRIDYL-LEEDER在微电子中电沉积铜

    公开(公告)号:WO2010062822A2

    公开(公告)日:2010-06-03

    申请号:PCT/US2009/065053

    申请日:2009-11-19

    Abstract: A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

    Abstract translation: 一种用于金属化半导体集成电路器件基板中的通孔特征的方法,其中所述半导体集成电路器件基板包括前表面,后表面和通孔特征,并且其中所述通孔特征包括在所述基板的前表面中的开口 ,从基板的前表面向内延伸的侧壁和底部。 该方法包括使半导体集成电路器件衬底与包含(a)铜离子源和(b)矫光剂化合物的电解铜沉积化学物质接触,其中矫光剂化合物是二吡啶基化合物和烷化剂的反应产物; 并向电解沉积化学物质提供电流以将铜金属沉积到通孔特征的底部和侧壁上,从而产生铜填充的通孔特征。

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