公开(公告)号：WO2015147801A1

公开(公告)日：2015-10-01

申请号：PCT/US2014031735

申请日：2014-03-25

Applicant: INTEL CORPORATON ,  MAJHI PRASHANT ,  KARPOV ELIJAH V ,  SHAH UDAY ,  MUKHERJEE NILOY ,  KUO CHARLES C ,  PILLARISETTY RAVI ,  DOYLE BRIAN S ,  CHAU ROBERT S

Inventor： MAJHI PRASHANT ,  KARPOV ELIJAH V ,  SHAH UDAY ,  MUKHERJEE NILOY ,  KUO CHARLES C ,  PILLARISETTY RAVI ,  DOYLE BRIAN S ,  CHAU ROBERT S

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

Abstract translation: 公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。 该技术可用于相对于给定存储器单元空间的平面电阻存储器单元来减少所涉及的形成电压要求和/或电阻（例如在低电阻状态期间的电阻）。 非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。 第二电极可以基本上在开关层的相对部分之间，并且在形成非平面电阻式存储单元之后，第一电极可以基本上与开关层的至少两侧相邻。 在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

公开(公告)号：WO1998000783A1

公开(公告)日：1998-01-08

申请号：PCT/US1997011163

申请日：1997-06-27

Applicant: INTEL CORPORATON

Inventor： INTEL CORPORATON ,  POISNER, David ,  RAMAN, Rajesh

IPC: G06F11/30

CPC classification number: G01R31/3004 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method and apparatus for controlling access to DMA control registers, specifically operating according to a Distributed Direct Memory Access (DDMA) protocol. When an access to a peripheral device (50a-c) ends in a Master Abort due to the failure of the peripheral device (50a-c) to respond to the DDMA Master component (43a) during a DDMA transaction, a System Management Interrupt (SMI#) is generated to the central processing unit (31). In the resulting execution of the System Management Mode code by the CPU (31), the cause of the peripheral component (50a-c) not responding (e.g., that the peripheral (50a-c) is in a low power mode, the connection between the DDMA Master (43a) and the peripheral (50a-c) is interrupted, etc.) is determined. The CPU (31), executing SMM code, takes steps to correct the problem. For example, if the peripheral (50a-c) is powered down, the CPU (31) will power it up so the DDMA transaction can subsequently occur.

Abstract translation: 一种用于控制对DMA控制寄存器的访问的方法和装置，具体根据分布式直接存储器访问（DDMA）协议进行操作。 当由于外围设备（50a-c）在DDMA事务期间对DDMA主组件（43a）的响应而导致外围设备（50a-c）的访问结束于主中止时，系统管理中断 SMI＃）生成到中央处理单元（31）。 在由CPU（31）执行的系统管理模式代码中，周边部件（50a-c）的原因不响应（例如，外围设备（50a-c）处于低功率模式），连接 DDMA主机（43a）和外围设备（50a-c）之间的中断等）被确定。 执行SMM代码的CPU（31）采取步骤来纠正问题。 例如，如果外围设备（50a-c）断电，则CPU（31）将为其供电，从而可以随后发生DDMA事务。