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    RESISTIVE RANDOM-ACCESS MEMORY INCLUDING TUNNEL SOURCE ACCESS TRANSISTOR
    3.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY INCLUDING TUNNEL SOURCE ACCESS TRANSISTOR 审中-公开

    公开(公告)号：WO2019005113A1

    公开(公告)日：2019-01-03

    申请号：PCT/US2017/040321

    申请日：2017-06-30

    Applicant: INTEL CORPORATION

    Inventor： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2418

    Abstract: Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on the bitcell transistor's source terminal using epitaxial growth. Accordingly, such RRAM bitcells are referred to herein as having a 1T(D)-1R configuration. As can be understood based on this disclosure, the tunnel diode's resistance is asymmetric with respect to RRAM write voltage. Thus, the tunnel diode optimizes array operations for the 1T(D)-1R bitcells described herein, enabling both control of current compliance in the SET direction and maximization of current in the RESET direction from the same RRAM bitcell. The 1T(D)-1R architecture is compatible with a multitude of RRAM device structures and transistor types, such as NMOS and PMOS configurations. Further, the tunnel diode can be integrated in a MOSFET access transistor without increasing cell layout area.

    HYBRID MEMORY DEVICES
    5.
    发明申请
    HYBRID MEMORY DEVICES 审中-公开
    混合存储设备

    公开(公告)号：WO2018067168A1

    公开(公告)日：2018-04-12

    申请号：PCT/US2016/055911

    申请日：2016-10-07

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： GE, Ning ,  SIMSKE, Steven J. ,  GEORGE, David

    IPC: G11C14/00

    CPC classification number: G11C14/0045 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/2436 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608

    Abstract: In some examples, a hybrid memory device includes multiple memory cells, where a given memory cell of the multiple memory cells includes a volatile memory element having a plurality of layers including electrically conductive layers and a dielectric layer between the electrically conductive layers, and a non-volatile resistive memory element to store different data states represented by respective different resistances of the non-volatile resistive memory element, the non-volatile resistive memory element having a plurality of layers including electrically conductive layers and a resistive switching layer between the electrically conductive layers of the non-volatile resistive memory element.

    Abstract translation: 在一些示例中，混合存储器件包括多个存储器单元，其中多个存储器单元中的给定存储器单元包括具有多个层的易失性存储器元件，所述多个层包括导电层和介电层 所述导电层和非易失性电阻式存储器元件以存储由所述非易失性电阻式存储器元件的相应不同电阻表示的不同数据状态，所述非易失性电阻存储器元件具有包括导电层的多个层和 非易失性电阻存储元件的导电层之间的电阻切换层。

    RESISTIVE RANDOM ACCESS MEMORY CELL WITH THREE TRANSISTORS AND TWO RESISTIVE MEMORY ELEMENTS
    6.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY CELL WITH THREE TRANSISTORS AND TWO RESISTIVE MEMORY ELEMENTS 审中-公开
    具有三个晶体管和两个电阻性存储元件的电阻式随机存取存储器单元

    公开(公告)号：WO2018063446A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/031795

    申请日：2017-05-09

    Applicant: MICROSEMI SOC CORP.

    Inventor： MC COLLUM, John, L. ,  HECHT, Volker

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C2013/0042 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436

    Abstract: A ReRAM cell array has rows and columns and includes first and second complementary bit lines for each row, a first, second and third word lines for each column and a source bit line for each row. A ReRAM cell at each row and column includes a first resistive memory element, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first resistive memory element, its drain connected to a switch node, its gate connected to the first word line of its column, a second resistive memory element, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second resistive memory element, its drain connected to the switch node, its gate connected to the second word line of its column, and a programming transistor having a drain connected to the switch node, a source connected to the source bit line of its row and a gate connected to the third word line of its column.

    Abstract translation: ReRAM单元阵列具有行和列，并且包括每行的第一和第二互补位线，每列的第一，第二和第三字线以及每行的源位线。 每行和每列的ReRAM单元包括第一电阻式存储器元件，其第一端连接到其行的第一互补位线，p沟道晶体管，其源极连接到第一电阻式存储器元件的第二端， 漏极连接到开关节点，其栅极连接到其列的第一字线，第二电阻式存储器元件，其第一端连接到其行的第二互补位线，n沟道晶体管，其源极连接到 第二电阻式存储器元件的第二端，其漏极连接到开关节点，其栅极连接到其列的第二字线，以及编程晶体管，其漏极连接到开关节点，源极连接到源位线 的行和连接到其列的第三个字线的门。

    CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH ENGINEERED SIDEWALLS FOR FILAMENT LOCALIZATION
    7.
    发明申请
    CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH ENGINEERED SIDEWALLS FOR FILAMENT LOCALIZATION 审中-公开
    导电桥随机访问存储器（CBRAM）器件，带有工程设计的侧壁用于光纤本地化

    公开(公告)号：WO2018004625A1

    公开(公告)日：2018-01-04

    申请号：PCT/US2016/040551

    申请日：2016-06-30

    Applicant: INTEL CORPORATION

    Inventor： MAJHI, Prashant ,  KARPOV, Elijah V. ,  SHAH, Uday ,  PILLARISETTY, Ravi ,  MUKHERJEE, Niloy ,  BIELEFELD, Jeffery D. ,  INDUKURI, Tejaswi K. ,  CLARKE, James S.

    IPC: H01L45/00

    CPC classification number: H01L45/00 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16

    Abstract: Approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewalls for filament localization, and the resulting structures and devices, are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect. A resistance switching layer is disposed on the first electrode layer. The resistance switching layer includes an electrolyte material having doped regions at outermost ends of the electrolyte material but not in a central portion of the electrolyte material. A metal ion source layer is disposed on the resistance switching layer. A second electrode layer is disposed on the metal ion source layer.

    Abstract translation: 描述了用于制造具有用于灯丝定位的工程侧壁的导电桥随机存取存储器（CBRAM）器件以及所得到的结构和器件的方法。 在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM器件还包括布置在导电互连上的CBRAM元件。 CBRAM元件包括设置在导电互连的最上表面上的第一电极层。 电阻切换层设置在第一电极层上。 电阻切换层包括电解质材料，该电解质材料在电解质材料的最外端具有掺杂区域，但不在电解质材料的中心部分。 金属离子源层设置在电阻切换层上。 第二电极层设置在金属离子源层上。

    APPROACHES FOR FABRICATING SELF-ALIGNED PEDESTALS FOR RRAM DEVICES AND THE RESULTING STRUCTURES
    8.
    发明申请
    APPROACHES FOR FABRICATING SELF-ALIGNED PEDESTALS FOR RRAM DEVICES AND THE RESULTING STRUCTURES 审中-公开
    用于制造RRAM器件自对准基座的方法及其结构

    公开(公告)号：WO2018004562A1

    公开(公告)日：2018-01-04

    申请号：PCT/US2016/040030

    申请日：2016-06-29

    Applicant: INTEL CORPORATION

    Inventor： MAJHI, Prashant ,  INDUKURI, Tejaswi K. ,  PILLARISETTY, Ravi ,  SHAH, Uday ,  MUKHERJEE, Niloy ,  KARPOV, Elijah V. ,  CLARKE, James S.

    IPC: G11C13/00 ,  H01L27/10 ,  H01L45/00

    CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/79 ,  H01L45/00 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1675

    Abstract: Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the conductive interconnect and in the ILD layer. The first electrode layer has an uppermost surface substantially co-planar with an uppermost surface of the ILD layer. A resistance switching layer is disposed on the uppermost surface of the first electrode layer and on a portion of the uppermost surface of the ILD layer. A second electrode layer is disposed on the resistance switching layer.

    Abstract translation: 描述了用于制造电阻随机存取存储器（RRAM）元件和器件的自对准基座以及所得到的结构的方法。 在一个示例中，电阻随机存取存储器（RRAM）器件包括布置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 RRAM元件设置在导电互连上。 RRAM元件包括设置在导电互连上和ILD层中的第一电极层。 第一电极层具有与ILD层的最上表面基本共面的最上表面。 电阻切换层设置在第一电极层的最上表面上和ILD层的最上表面的一部分上。 第二电极层设置在电阻切换层上。

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