公开(公告)号：WO2003001584A1

公开(公告)日：2003-01-03

申请号：PCT/US2002/019789

申请日：2002-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  JAGANNATHAN, Basanth ,  JENG, Shwu-Jen ,  JOHNSON, Jeffrey, B. ,  JOHNSON, Robb, A. ,  LANZEROTTI, Louis, D. ,  STEIN, Kenneth, J. ,  SUBBANNA, Seshadri

Inventor： JAGANNATHAN, Basanth ,  JENG, Shwu-Jen ,  JOHNSON, Jeffrey, B. ,  JOHNSON, Robb, A. ,  LANZEROTTI, Louis, D. ,  STEIN, Kenneth, J. ,  SUBBANNA, Seshadri

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract translation: 一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口 叠加。 这通过使发射器基座（66）比发射器开口更宽来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

公开(公告)号：WO2006034189A3

公开(公告)日：2006-05-04

申请号：PCT/US2005033472

申请日：2005-09-19

Applicant: IBM ,  ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/737 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/739 ,  H01L29/76

CPC classification number: H01L29/0653 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor (100) and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode (165) formed on a top surface (170) of a gate dielectric layer (155), the gate dielectric layer on a top surface (160) of a single-crystal silicon channel region (110), the single-crystal silicon channel region on a top surface of a Ge including layer (135), the Ge including layer on a top surface of a single-crystal silicon substrate (150), the Ge including layer between a first dielectric layer (215A) and a second dielectric layer (215B) on the top surface of the single-crystal silicon substrate.

Abstract translation: 场效应晶体管（100）和制造该场效应晶体管的方法。 该场效应晶体管包括：形成在栅极电介质层（155）的顶表面（170）上的栅电极（165），单晶硅沟道区（155）的顶表面（160）上的栅电介质层 110），在包括Ge的层（135）的顶表面上的单晶硅沟道区，在单晶硅衬底（150）的顶表面上的包含Ge的层，在第一电介质 在所述单晶硅衬底的顶表面上的第一电介质层（215A）和第二电介质层（215B）。

公开(公告)号：WO2006034189A2

公开(公告)日：2006-03-30

申请号：PCT/US2005/033472

申请日：2005-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ANDERSON, Brent, A. ,  LANZEROTTI, Louis, D. ,  NOWAK, Edward J.

Inventor： ANDERSON, Brent, A. ,  LANZEROTTI, Louis, D. ,  NOWAK, Edward J.

IPC: G06F11/00

CPC classification number: H01L29/0847 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor (100) and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode (165) formed on a top surface (170) of a gate dielectric layer (155), the gate dielectric layer on a top surface (160) of a single-crystal silicon channel region (110), the single-crystal silicon channel region on a top surface of a Ge including layer (135), the Ge including layer on a top surface of a single-crystal silicon substrate (150), the Ge including layer between a first dielectric layer (215A) and a second dielectric layer (215B) on the top surface of the single-crystal silicon substrate.

Abstract translation: 场效应晶体管（100）和制造场效应晶体管的方法。 该场效应晶体管包括：形成在栅介质层（155）的顶表面（170）上的栅电极（165），在单晶硅沟道区（160）的顶表面（160）上的栅介质层 110），包含Ge的层（135）的顶表面上的单晶硅沟道区域，单晶硅衬底（150）的顶表面上的Ge包括层，在第一电介质 层（215A）和在单晶硅衬底的顶表面上的第二电介质层（215B）。

公开(公告)号：WO2003092079A1

公开(公告)日：2003-11-06

申请号：PCT/US2002/013315

申请日：2002-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  JOHNSON, Robb, Allen ,  LANZEROTTI, Louis, D.

Inventor： JOHNSON, Robb, Allen ,  LANZEROTTI, Louis, D.

IPC: H01L31/0328

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

Abstract: A bipolar transistor for a small signal amplifier that has improved Early voltages, and hence enhanced cutoff frequency. The SiGe layer (14) has a thickness (t) and a Ge content that is greater than the stability limit. The misfit dislocations do not create appreciable charge trapping sites, and do not extend into the overlying base/collector junction, such that performance is improved without yield degradation.

Abstract translation: 一种用于小信号放大器的双极晶体管，其具有改进的早期电压，并因此提高了截止频率。 SiGe层（14）的厚度（t）和Ge含量大于稳定极限。 失配位错不产生明显的电荷捕获位点，并且不扩展到上覆的基极/集电极结，使得性能得到改善而不降低产率。