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    ADJUSTMENT OF MEMORY WRITE TIMING BASED ON ERROR DETECTION TECHNIQUES
    1.
    发明申请
    ADJUSTMENT OF MEMORY WRITE TIMING BASED ON ERROR DETECTION TECHNIQUES 审中-公开
    基于错误检测技术调整存储器写入时序

    公开(公告)号：WO2011031847A1

    公开(公告)日：2011-03-17

    申请号：PCT/US2010/048252

    申请日：2010-09-09

    Applicant: ADVANCED MICRO DEVICES, INC. ,  NYGREN, Aaron, J. ,  LEE, Ming-ju, E. ,  BARAKAT, Shadi, M. ,  XU, Xiaoling ,  PHAM, Toan, D. ,  KRUGER, Warren, Fritz

    Inventor： NYGREN, Aaron, J. ,  LEE, Ming-ju, E. ,  BARAKAT, Shadi, M. ,  XU, Xiaoling ,  PHAM, Toan, D. ,  KRUGER, Warren, Fritz

    IPC: G06F13/42

    CPC classification number: G06F13/4243

    Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

    Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

    FAST TRANSITION FROM LOW-SPEED MODE TO HIGH-SPEED MODE IN HIGH-SPEED INTERFACES
    3.
    发明申请
    FAST TRANSITION FROM LOW-SPEED MODE TO HIGH-SPEED MODE IN HIGH-SPEED INTERFACES 审中-公开
    从高速模式到高速接口的高速模式的快速切换

    公开(公告)号：WO2007136785A3

    公开(公告)日：2008-05-02

    申请号：PCT/US2007011964

    申请日：2007-05-17

    Applicant: ATI TECHNOLOGIES INC ,  MACRI JOSEPH ,  MOREIN STEPHEN ,  LEE MING-JU E ,  CHEN LIN

    Inventor： MACRI JOSEPH ,  MOREIN STEPHEN ,  LEE MING-JU E ,  CHEN LIN

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

    Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

    Abstract translation: 描述了针对在模拟定时电路初始化和变得可用的时间段期间继续以低功率模式工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。

    ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES
    4.
    发明申请
    ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
    使用专用接口线的高速非对称接口中的错误检测

    公开(公告)号：WO2007054808A3

    公开(公告)日：2007-10-04

    申请号：PCT/IB2006003180

    申请日：2006-11-10

    Applicant: ADVANCED MICRO DEVICES INC ,  MACRI JOSEPH ,  MOREIN STEPHEN ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  CHEN LIN

    Inventor： MACRI JOSEPH ,  MOREIN STEPHEN ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  CHEN LIN

    IPC: H04L1/00 ,  G06F11/08

    CPC classification number: H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

    Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

    Abstract translation: 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的一行接口从第二个组件接收一个签名，并通过该接口与READ和WRITE操作同时进行。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

    FAST TRANSITION FROM LOW-SPEED MODE TO HIGH-SPEED MODE IN HIGH-SPEED INTERFACES
    5.
    发明申请
    FAST TRANSITION FROM LOW-SPEED MODE TO HIGH-SPEED MODE IN HIGH-SPEED INTERFACES 审中-公开
    从高速模式到高速接口的高速模式的快速切换

    公开(公告)号：WO2007136785A2

    公开(公告)日：2007-11-29

    申请号：PCT/US2007/011964

    申请日：2007-05-17

    Applicant: ATI TECHNOLOGIES, INC. ,  MACRI, Joseph ,  MOREIN, Stephen ,  LEE, Ming-Ju, E. ,  CHEN, Lin

    Inventor： MACRI, Joseph ,  MOREIN, Stephen ,  LEE, Ming-Ju, E. ,  CHEN, Lin

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

    Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

    Abstract translation: 描述了针对在模拟定时电路初始化和变得可用的时间段期间继续以低功率模式工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。

    ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES
    7.
    发明申请
    ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES USING DEDICATED INTERFACE LINES 审中-公开
    高速不对称接口中使用专用接口线的误差检测

    公开(公告)号：WO2007054808A2

    公开(公告)日：2007-05-18

    申请号：PCT/IB2006/003180

    申请日：2006-11-10

    Applicant: ADVANCED MICRO DEVICES, INC ,  MACRI, Joseph ,  MOREIN, Stephen ,  GAUTHIER, Claude ,  LEE, Ming-Ju, E. ,  CHEN, Lin

    Inventor： MACRI, Joseph ,  MOREIN, Stephen ,  GAUTHIER, Claude ,  LEE, Ming-Ju, E. ,  CHEN, Lin

    IPC: H04L1/00 ,  G06F11/08

    CPC classification number: H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

    Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

    Abstract translation: 描述了用于检测高速不对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件明显比第二组件更智能。 第一个组件通过接口的一行接收来自第二个组件的签名，并通过该接口进行READ和WRITE操作。 与从第二组件到第一组件签名的传输相关联的等待时间是第二组件计算签名所用的时间。 将收到的签名与第一个组件存储的签名进行比较。 这两个签名都对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

    ASYMMETRICAL IO METHOD AND SYSTEM
    9.
    发明申请
    ASYMMETRICAL IO METHOD AND SYSTEM 审中-公开
    不对称IO方法和系统

    公开(公告)号：WO2007035345A1

    公开(公告)日：2007-03-29

    申请号：PCT/US2006/035627

    申请日：2006-09-13

    Applicant: ATI TECHNOLOGIES, INC. ,  MOREIN, Stephen ,  MACRI, Joseph ,  GAUTHIER, Claude ,  LEE, Ming-Ju, E. ,  CHEN, Lin

    Inventor： MOREIN, Stephen ,  MACRI, Joseph ,  GAUTHIER, Claude ,  LEE, Ming-Ju, E. ,  CHEN, Lin

    IPC: H04L7/00 ,  G06F13/42

    CPC classification number: H04L7/02 ,  H04L7/0025 ,  H04L7/0091

    Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

    Abstract translation: 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

    ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES
    10.
    发明申请
    ERROR DETECTION IN HIGH SPEED ASYMMETRIC INTERFACES 审中-公开
    高速不对称接口中的误差检测

    公开(公告)号：WO2007052147A2

    公开(公告)日：2007-05-10

    申请号：PCT/IB2006003113

    申请日：2006-11-02

    Applicant: ADVANCED MICRO DEVICES INC ,  MACRI JOSEPH ,  MOREIN STEPHEN ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  CHEN LIN

    Inventor： MACRI JOSEPH ,  MOREIN STEPHEN ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  CHEN LIN

    CPC classification number: G06F11/10

    Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

    Abstract translation: 描述了用于检测高速不对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件明显比第二组件更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有线路从第二个组件接收签名。 将收到的签名与第一个组件存储的签名进行比较。 两个签名都对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要指示第二个组件。

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