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    SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS
    1.
    发明申请
    SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开
    具有多个半导体层的半导体器件

    公开(公告)号：WO2006001915A2

    公开(公告)日：2006-01-05

    申请号：PCT/US2005016253

    申请日：2005-05-11

    Applicant: FREESCALE SEMICONDUCTOR INC ,  VENKATESAN SURESH ,  FOISY MARK C ,  MENDICINO MICHAEL A ,  ORLOWSKI MARIUS K

    Inventor： VENKATESAN SURESH ,  FOISY MARK C ,  MENDICINO MICHAEL A ,  ORLOWSKI MARIUS K

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L27/1203

    Abstract: A semiconductor device structure (10) uses two semiconductor layers (16 & 20) to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors (38) when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors (40) preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers (16 & 20), both the N and P channel transistors (38 & 40) can be optimized for carrier mobility.

    Abstract translation: 半导体器件结构（10）使用两个半导体层（16和20）分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。 用于确定它的导电特性是半导体的材料类型，晶面，取向和应变的组合。 当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管（38）的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。 或者，晶面可以是（111），在这种情况下的取向是不重要的。 用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管（40）优选具有拉伸应变，硅半导体材料和（100）平面。 利用分离的半导体层（16和20），N和P沟道晶体管（38和40）都可以针对载流子迁移率进行优化。

    SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES AND METHOD THEREFOR
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES AND METHOD THEREFOR 审中-公开
    具有电气接触的半导体器件及其方法

    公开(公告)号：WO2005020279A2

    公开(公告)日：2005-03-03

    申请号：PCT/US2004/022437

    申请日：2004-07-13

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  SANCHEZ, Hector ,  MENDICINO, Michael, A. ,  MIN, Byoung, W. ,  YU, Kathleen, C.

    Inventor： SANCHEZ, Hector ,  MENDICINO, Michael, A. ,  MIN, Byoung, W. ,  YU, Kathleen, C.

    IPC: H01L

    CPC classification number: H01L27/0688 ,  H01L21/76838 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

    Abstract translation: 半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连件（68）连接的直接下伏的无源器件，例如电容器（75,77,79） ，99）。 通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并接触电容器电极的第一（75）。 横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。 可以使用金属互连或导电材料（68）作为通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

    SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开

    公开(公告)号：WO2006001915A3

    公开(公告)日：2006-01-05

    申请号：PCT/US2005/016253

    申请日：2005-05-11

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  VENKATESAN, Suresh ,  FOISY, Mark, C. ,  MENDICINO, Michael, A. ,  ORLOWSKI, Marius, K.

    Inventor： VENKATESAN, Suresh ,  FOISY, Mark, C. ,  MENDICINO, Michael, A. ,  ORLOWSKI, Marius, K.

    IPC: H01L29/04

    Abstract: A semiconductor device structure (10) uses two semiconductor layers (16 & 20) to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors (38) when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors (40) preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers (16 & 20), both the N and P channel transistors (38 & 40) can be optimized for carrier mobility.

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