公开(公告)号：WO2022200338A1

公开(公告)日：2022-09-29

申请号：PCT/EP2022/057471

申请日：2022-03-22

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： ARANGO, Yulieth ,  ROMANO, Gianpaolo ,  MIHAILA, Andrei ,  BELLINI, Marco ,  KNOLL, Lars

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423

Abstract: In at least one embodiment, the power semiconductor device (1) comprises - a semiconductor body (2), - at least one source region (21) of a first conductivity type, - at least one channel region (22) of a second conductivity type below the at least one source region (21), - a drift region (23) of the first conductivity type below the at least one channel region (22), and - at least one trench (4) running from a top side (20) of the semiconductor body (2) through the at least one source region (21) and through the at least one channel region (22) and ending in the drift region (23), wherein - the at least one trench (4) accommodates a gate electrode (34), and - seen in top view of the top side (20), the at least one trench (4) comprises non-linearly running side walls (44).

公开(公告)号：WO2021163230A1

公开(公告)日：2021-08-19

申请号：PCT/US2021/017514

申请日：2021-02-10

Applicant: SLT TECHNOLOGIES, INC.

Inventor： CARDWELL, Drew ,  D'EVELYN, Mark P.

IPC: H01L21/02 ,  C30B29/38 ,  C30B29/40 ,  H01L29/04 ,  H01L29/20

Abstract: Embodiments of the present disclosure include techniques related to techniques for processing materials for manufacture of group-ill metal nitride and gallium based substrates. More specifically, embodiments of the disclosure include techniques for growing large area substrates using a combination of processing techniques. Merely by way of example, the disclosure can be applied to growing crystals of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others for manufacture of bulk or patterned substrates. Such bulk or patterned substrates can be used for a variety of applications including optoelectronic and electronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photodetectors, integrated circuits, and transistors, and others.

公开(公告)号：WO2020167384A1

公开(公告)日：2020-08-20

申请号：PCT/US2019/068946

申请日：2019-12-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： KONSTANTINOV, Andrei

IPC: H01L29/872 ,  H01L21/329 ,  H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L29/04

Abstract: SiC Schottky rectifiers with surge current ruggedness are described that may be configured to provide multiple types of surge current protection. Different current magnitudes and characteristics may be associated with the different types of surge current events. The described Schottky rectifier structures provide surge current protection in multiple types of surge current scenarios, while minimizing or reducing situations in which solution techniques in one context undesirably mitigate effects of solution techniques in another context.

公开(公告)号：WO2020106974A1

公开(公告)日：2020-05-28

申请号：PCT/US2019/062642

申请日：2019-11-21

Applicant: SKORPIOS TECHNOLOGIES, INC.

Inventor： APIRATIKUL, Paveen ,  LAMBERT, Damien

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/12 ,  H01L33/04

Abstract: An exemplary multi quantum well structure may include a silicon platform having a pit formed in the silicon platform, a chip positioned inside the pit, a first waveguide formed in the chip, and a second waveguide formed in the silicon platform. The pit may be defined at least in part by a sidewall and a base. The chip may include a first side and a first recess in the first side. The first side may be defined in part by a first cleaved or diced facet. The first recess may be defined in part by a first etched facet. The first waveguide may be configured to guide an optical beam to pass through the first etched facet. The second waveguide may be configured to guide the optical beam to pass through the sidewall. The second waveguide may be optically aligned with the first waveguide.

公开(公告)号：WO2019222458A1

公开(公告)日：2019-11-21

申请号：PCT/US2019/032602

申请日：2019-05-16

Applicant: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY ,  FRAUNHOFER USA

Inventor： GROTJOHN, Timothy, A. ,  DIAZ, Ramon ,  HARDY, Aaron

IPC: H01L21/02 ,  H01L29/00 ,  H01L29/02 ,  H01L29/04 ,  H01L29/12 ,  C23C16/27 ,  C30B25/00 ,  C30B25/18 ,  C30B29/04

Abstract: The disclosure relates to large area single crystal diamond (SCD) surfaces and substrates, and their methods of formation. Typical large area substrates can be at least about 25 mm, 50 mm, or 100 mm in diameter or square edge length, and suitable thicknesses can be about 100 µm to 1000 µm. The large area substrates have a high degree of crystallographic alignment. The large area substrates can be used in a variety of electronics and/or optics applications. Methods of forming the large area substrates generally include lateral and vertical growth of SCD on spaced apart and crystallographically aligned SCD seed substrates, with the individual SCD growth layers eventually merging to form a composite SCD layer of high quality and high crystallographic alignment. A diamond substrate holder can be used to crystallographically align the SCD seed substrates and reduce the effect of thermal stress on the formed SCD layers.

公开(公告)号：WO2019116464A1

公开(公告)日：2019-06-20

申请号：PCT/JP2017/044737

申请日：2017-12-13

Applicant: 日産自動車株式会社

Inventor： 倪　威 ,  林　哲也 ,  丸井　俊治 ,  田中　亮太 ,  竹本　圭佑

IPC: H01L21/338 ,  H01L29/04 ,  H01L29/06 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872

CPC classification number: H01L29/04 ,  H01L29/06 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872

Abstract: 半導体装置は、互いに対向する第１主面及び第２主面を有し、第１主面に溝（９）が形成された基板（１）と、溝（９）の表面に接して形成される半導体領域（２）と、半導体領域（２）の表面に接して形成され、半導体領域（２）に二次元電子ガス層（２ａ）を発生させる電子供給領域（３）と、を備える。また、半導体装置は、二次元電子ガス層（２ａ）と電気的に接続する第一電極（６）と、第一電極（６）と離間した位置で二次元電子ガス層（２ａ）と電気的に接続する第二電極（７）と、を備える。半導体領域（２）は、溝（９）において、互いに対面する第１側面（９ａ）と第２側面（９ｂ）のうち、第１側面（９ａ）のみに形成される。

公开(公告)号：WO2019113045A1

公开(公告)日：2019-06-13

申请号：PCT/US2018/063817

申请日：2018-12-04

Applicant: QROMIS, INC.

Inventor： ODNOBLYUDOV, Vladimir ,  RISBUD, Dilip ,  AKTAS, Ozgur ,  BASCERI, Cem

IPC: H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78

Abstract: A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.

公开(公告)号：WO2019013939A1

公开(公告)日：2019-01-17

申请号：PCT/US2018/038614

申请日：2018-06-20

Applicant: ARES MATERIALS INC.

Inventor： REIT, Radu ,  AVENDANO-BOLIVAR, Adrian ,  VOUTSAS, Apostolos ,  ARREAGA-SALAS, David

IPC: H01L29/04

CPC classification number: H01L29/78636 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/7869

Abstract: Provided is a method for forming an organic planarization layer. The method includes forming lithographically-patterned arrays atop a substrate; disposing a thiol-based photocurable resin on to the lithographically-patterned arrays to form a photocurable planarization layer; and curing the photocurable planarization layer to form a flat surface above the lithographically-patterned array.

公开(公告)号：WO2019013136A1

公开(公告)日：2019-01-17

申请号：PCT/JP2018/025767

申请日：2018-07-06

Applicant: 株式会社FLOSFIA

Inventor： 杉本　雅裕 ,  ▲高▼橋　勲 ,  神原　仁志 ,  四戸　孝 ,  人羅　俊実

IPC: H01L29/872 ,  H01L29/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/47 ,  H01L29/861 ,  H01L29/868

Abstract: 特にパワーデバイスに有用な半導体特性に優れた半導体装置を提供する。半導体領域と、該半導体領域上に設けられているバリア電極とを少なくとも備えている半導体装置であって、前記半導体領域と前記バリア電極との間に、前記半導体領域と前記バリア電極との界面におけるバリアハイトよりも前記バリア電極とのバリアハイトが大きくなるバリアハイト調整領域が設けられており、前記バリアハイト調整領域が前記半導体領域表面に複数埋め込まれている半導体装置。

公开(公告)号：WO2018182685A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025355

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： KIM, Raseong ,  AVCI, Uygar, E. ,  YOUNG, Ian, A.

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161

Abstract: Embodiments are generally directed to Germanium CMOS (Complementary Metal-Oxide Semiconductor) structures with optimized quantum confinement and multiple threshold voltage operation. An embodiment of a CMOS device includes one or both of: one or more nMOS devices (n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors)) or one or more pMOS devices (p-type MOSFETs). Each of each of the one or more nMOS devices or one or more pMOS devices includes a Germanium or Germanium alloy channel, a quantum confined channel structure, an optimum crystal orientation for the quantum confined channel structure, and a plurality of threshold voltage options.