公开(公告)号：WO2014077902A1

公开(公告)日：2014-05-22

申请号：PCT/US2013/045025

申请日：2013-06-10

Applicant: INTEL CORPORATION ,  MOZAK, Christopher P. ,  NAVARATNAM, Navindra ,  ELASSAL, Mahmoud ,  MOZAK, Christopher P.

Inventor： MOZAK, Christopher P. ,  NAVARATNAM, Navindra ,  ELASSAL, Mahmoud ,  MOZAK, Christopher P.

IPC: G05F1/10 ,  G05F1/565

CPC classification number: G05F1/10 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/105 ,  H02M3/07 ,  H02M2003/1566

Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a "too high" signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a "too low" signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.

Abstract translation: 电路提供电源电压。 电压调节器被耦合以接收目标参考信号。 电压调节器产生电源电压（Vtt）并被耦合以接收电源电压作为输入信号。 当电源电压超过上限阈值时，上限比较器接收高于目标参考电压信号和电源电压的上限电压信号，以产生“过高”信号。 下限比较器接收低于目标参考电压信号的下限电压信号和电源电压，以在电源电压低于下阈值时产生“太低”信号。 耦合上拉电流源以响应于太低的信号将电源电压拉高。 耦合下拉电流源以响应于太高的信号而将电源电压降低。

公开(公告)号：WO2011081843A2

公开(公告)日：2011-07-07

申请号：PCT/US2010/059823

申请日：2010-12-10

Applicant: INTEL CORPORATION ,  SPRY, Bryan L. ,  SCHOENBORN, Theodore Z. ,  ABRAHAM, Philip ,  MOZAK, Christopher P. ,  ELLIS, David G. ,  NEJEDLO, Jay J. ,  QUERBACH, Bruce ,  GREENFIELD, Zvika ,  GHATTAS, Rony ,  THOLIYIL, Jayasekhar ,  LUCAS, Charles D. ,  YUNKER, Christopher E.

Inventor： SPRY, Bryan L. ,  SCHOENBORN, Theodore Z. ,  ABRAHAM, Philip ,  MOZAK, Christopher P. ,  ELLIS, David G. ,  NEJEDLO, Jay J. ,  QUERBACH, Bruce ,  GREENFIELD, Zvika ,  GHATTAS, Rony ,  THOLIYIL, Jayasekhar ,  LUCAS, Charles D. ,  YUNKER, Christopher E.

IPC: G11C29/10

CPC classification number: G11C29/08 ,  G11C29/10 ,  G11C29/44

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract translation: 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。

公开(公告)号：WO2014004748A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/048016

申请日：2013-06-26

Applicant: INTEL CORPORATION ,  BAINS, Kuljit ,  HALBERT, John B. ,  MOZAK, Christopher P. ,  SCHOENBORN, Theodore Z. ,  GREENFIELD, Zvika

Inventor： BAINS, Kuljit ,  HALBERT, John B. ,  MOZAK, Christopher P. ,  SCHOENBORN, Theodore Z. ,  GREENFIELD, Zvika

IPC: G11C11/401 ,  G11C11/406

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as "hammered" or a "row hammer event"), physically adjacent row (a "victim" row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：WO2011163420A3

公开(公告)日：2012-04-19

申请号：PCT/US2011041530

申请日：2011-06-22

Applicant: INTEL CORP ,  MOZAK CHRISTOPHER P ,  ZIA VICTOR

Inventor： MOZAK CHRISTOPHER P ,  ZIA VICTOR

IPC: G11C5/14

CPC classification number: H01L27/0285

Abstract: Described herein are a method, apparatus, and system for electrostatic discharge protection of supplies. The apparatus comprises a timer unit having a node with a first supply signal and operable to generate a first timer signal based on the first supply signal; and a clamp unit, coupled to the timer unit and having a node with a second supply signal, operable to clamp the second supply signal in response to electrostatic discharge (ESD) on the node with the second supply signal for a duration based on a signal level of the first timer signal.

Abstract translation: 这里描述了用于电源的静电放电保护的方法，装置和系统。 该装置包括具有第一电源信号的节点的定时器单元，用于基于第一电源信号产生第一定时器信号; 以及钳位单元，其耦合到所述定时器单元并具有具有第二电源信号的节点，用于响应于具有所述第二电源信号的所述节点上的静电放电（ESD）钳位所述第二电源信号，所述持续时间基于信号 第一定时器信号的电平。

公开(公告)号：WO2011163420A2

公开(公告)日：2011-12-29

申请号：PCT/US2011/041530

申请日：2011-06-22

Applicant: INTEL CORPORATION ,  MOZAK, Christopher, P. ,  ZIA, Victor

Inventor： MOZAK, Christopher, P. ,  ZIA, Victor

IPC: G11C5/14

CPC classification number: H01L27/0285

Abstract: Described herein are a method, apparatus, and system for electrostatic discharge protection of supplies. The apparatus comprises a timer unit having a node with a first supply signal and operable to generate a first timer signal based on the first supply signal; and a clamp unit, coupled to the timer unit and having a node with a second supply signal, operable to clamp the second supply signal in response to electrostatic discharge (ESD) on the node with the second supply signal for a duration based on a signal level of the first timer signal.

Abstract translation: 这里描述了用于电源的静电放电保护的方法，装置和系统。 该装置包括具有第一电源信号的节点的定时器单元，用于基于第一电源信号产生第一定时器信号; 以及钳位单元，其耦合到所述定时器单元并具有具有第二电源信号的节点，用于响应于具有所述第二电源信号的所述节点上的静电放电（ESD）钳位所述第二电源信号，所述持续时间基于信号 第一定时器信号的电平。

公开(公告)号：WO2011153096A2

公开(公告)日：2011-12-08

申请号：PCT/US2011038361

申请日：2011-05-27

Applicant: INTEL CORP ,  MOSALIKANTI PRAVEEN ,  KURD NASSER A ,  MOZAK CHRISTOPHER P

Inventor： MOSALIKANTI PRAVEEN ,  KURD NASSER A ,  MOZAK CHRISTOPHER P

IPC: G11C8/00 ,  G11C7/22 ,  H03L7/081

CPC classification number: G06F1/324 ,  G06F1/3296 ,  H03L7/0802 ,  H03L7/0812 ,  H03L7/10 ,  H03L7/143 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.

Abstract translation: 提出了低功耗延迟锁定环（DLL）。 在一个实施例中，DLL包括相位检测器，其包括参考输入和用于确定相位差的反馈输入。 DLL还包括控制器，用于确定是否向参考输入和反馈输入提供信号，使得参考输入和反馈输入例如在低功率操作期间接收相同的输入。

公开(公告)号：WO2014209378A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048669

申请日：2013-06-28

Applicant: MOZAK, Christopher P. ,  ELASSAL, Mahmoud ,  INTEL CORPORATION

Inventor： MOZAK, Christopher P. ,  ELASSAL, Mahmoud

IPC: G05F1/10 ,  G05B11/01

CPC classification number: G06F1/26

Abstract: Described is a voltage regulator with feed-forward and feedback control. Described is an apparatus which comprises: a circuit for providing power or ground supply for a target circuit in response to a control signal; and a feed-forward filter to receive data and to generate the control signal according to the received data.

Abstract translation: 描述了具有前馈和反馈控制的电压调节器。 描述了一种装置，其包括：用于响应于控制信号为目标电路提供电力或接地电源的电路; 以及前馈滤波器，用于接收数据并根据接收到的数据产生控制信号。

公开(公告)号：WO2014105134A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046406

申请日：2013-06-18

Applicant: INTEL CORPORATION ,  KOSTINSKY, Alexey ,  GREENFIELD, Zvika ,  MOZAK, Christopher P. ,  KONEV, Pavel ,  FOMENKO, Olga

Inventor： KOSTINSKY, Alexey ,  GREENFIELD, Zvika ,  MOZAK, Christopher P. ,  KONEV, Pavel ,  FOMENKO, Olga

IPC: G06F13/14 ,  G06F12/00 ,  G11C11/4096

CPC classification number: G11C7/1072 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

Abstract translation: 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 引脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。

公开(公告)号：WO2013165350A1

公开(公告)日：2013-11-07

申请号：PCT/US2012/035784

申请日：2012-04-30

Applicant: INTEL CORPORATION ,  COX, Christopher E. ,  LOOP, Rebecca Z. ,  MOZAK, Christopher P.

Inventor： COX, Christopher E. ,  LOOP, Rebecca Z. ,  MOZAK, Christopher P.

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/161 ,  G06F13/1684 ,  G06F13/1694 ,  G06F13/382 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a system on a chip (SoC) includes a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller. The memory controller may be configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，芯片上的系统（SoC）包括多个处理器核心和存储器控制器，用于控制SoC与耦合到存储器控制器的存储器之间的通信。 存储器控制器可以被配置为向第一类型的存储器件发送镜像命令和地址信号，并将非镜像控制和地址信号发送到第二类型的存储器件。 描述和要求保护其他实施例。

公开(公告)号：WO2011153096A3

公开(公告)日：2011-12-08

申请号：PCT/US2011/038361

申请日：2011-05-27

Applicant: INTEL CORPORATION ,  MOSALIKANTI, Praveen ,  KURD, Nasser A. ,  MOZAK, Christopher P.

Inventor： MOSALIKANTI, Praveen ,  KURD, Nasser A. ,  MOZAK, Christopher P.

IPC: G11C8/00 ,  G11C7/22 ,  H03L7/081

Abstract: A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.