公开(公告)号：WO2009133553A1

公开(公告)日：2009-11-05

申请号：PCT/IL2009/000449

申请日：2009-04-27

Applicant: SANDISK IL LTD. ,  MURIN, Mark ,  LASSER, Menahem

Inventor： MURIN, Mark ,  LASSER, Menahem

IPC: G11C29/02 ,  G11C29/50 ,  G11C11/56

CPC classification number: G11C29/02 ,  G11C11/5628 ,  G11C16/04 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004

Abstract: A non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non- volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, (Vpgtn,vV) performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages (Vpgm, Vv) is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

Abstract translation: 使用对设备定制的电压和/或设备的部分（诸如非易失性存储元件的块或字线）访问非易失性存储器件。 访问可以包括编程，验证或阅读。 通过定制电压，可以优化（Vpgtn，vV）性能，包括寻址由程序干扰引起的阈值电压变化。 在一种方法中，存储器件中的不同存储元件组被编程为随机测试数据。 确定不同组的存储元件的阈值电压分布。 基于阈值电压分布来确定一组电压（Vpgm，Vv），并将其存储在非易失性存储位置中，用于随后用于访问不同组的存储元件。 可以在制造时确定该组电压以供随后在最终用户访问数据中使用。

公开(公告)号：WO2007046084A3

公开(公告)日：2007-04-26

申请号：PCT/IL2006/001175

申请日：2006-10-15

Applicant: RAMOT AT TEL-AVIV UNIVERSITY LTD. ,  LITSYN, Simon ,  ALROD, Idan ,  SHARON, Eran ,  MURIN, Mark ,  LASSER, Menachem

Inventor： LITSYN, Simon ,  ALROD, Idan ,  SHARON, Eran ,  MURIN, Mark ,  LASSER, Menachem

IPC: G11C29/00 ,  H03M13/00

Abstract: Data that are stored in cells of a multi-bit-per cell memory (42) according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non- systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

公开(公告)号：WO2006064497A3

公开(公告)日：2006-12-07

申请号：PCT/IL2005001341

申请日：2005-12-13

Applicant: MILSYS LTD ,  MURIN MARK ,  LASSER MENACHEM

Inventor： MURIN MARK ,  LASSER MENACHEM

IPC: G11C11/34

CPC classification number: G11C16/102 ,  G06F3/0626 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628

Abstract: Sectors of data are stored in a non-volatile memory (12) by writing all the sectors in a first order and subsequently writing all the sectors in a different, second order that is determined prior to the second writing. Sectors are stored in a non-volatile memory (12) by writing the sectors using a first set of write operations and again writing the sectors using a second set of write operations that write one or more of the sectors twice. The first set writes each sector only once and the second set writes the sectors from outside the memory (12). The first set writes in a mode that couples the cells of the memory (12) less than the second set. The first set writes less reliably than the second set.

Abstract translation: 数据的扇区通过以第一顺序写入所有扇区并随后以在第二次写入之前确定的不同的第二阶段写入所有扇区来存储在非易失性存储器（12）中。 扇区通过使用第一组写入操作写入扇区来存储在非易失性存储器（12）中，并且再次使用写入一个或多个扇区两次的第二写入操作来写入扇区。 第一组写入每个扇区一次，第二组从存储器（12）外部写入扇区。 第一组以一种将存储器（12）的单元小于第二组的模式写入。 第一组写入的可靠性低于第二组。

公开(公告)号：WO2010125436A1

公开(公告)日：2010-11-04

申请号：PCT/IB2010/000858

申请日：2010-04-17

Applicant: SANDISK IL, LTD. ,  MOSEK, Amir ,  LASSER, Menahem ,  MURIN, Mark

Inventor： MOSEK, Amir ,  LASSER, Menahem ,  MURIN, Mark

IPC: G06F12/02 ,  G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G06F2212/214

Abstract: The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non- volatile storage device operatively coupled to a host device. In some embodiments, data is stored to a cache area of a non-volatile memory within the peripheral non-volatile storage device in accordance with a historical rate at which other data was received by the peripheral storage device from the host device and/or a historical average time interval between successive host write requests received and/or an assessed rate at which data is required to be written to the non-volatile memory and/or a detecting by the peripheral non-volatile memory device that the host has read the storage ready/busy flag. In some embodiments, data is copied from a cache storage area of the non- volatile memory to a main storage area in accordance with the historical rate and/or the historical average time interval.

Abstract translation: 本公开涉及用于在可操作地耦合到主机设备的外围非易失性存储设备中实现高速缓存策略和/或缓存刷新策略的方法，设备和计算机可读介质。 在一些实施例中，根据外围存储设备从主机设备接收其他数据的历史速率和/或一个或多个存储器，数据被存储到外围非易失性存储设备内的非易失性存储器的高速缓存区域 接收的连续主机写入请求和/或需要将数据写入非易失性存储器的评估速率和/或由外围非易失性存储器设备检测到主机已读取存储器的历史平均时间间隔 准备/忙碌标志 在一些实施例中，根据历史速率和/或历史平均时间间隔将数据从非易失性存储器的高速缓存存储区域复制到主存储区域。

公开(公告)号：WO2009083954A1

公开(公告)日：2009-07-09

申请号：PCT/IL2008/001632

申请日：2008-12-17

Applicant: SANDISK IL LTD. ,  SHLICK, Mark ,  MURIN, Mark ,  LASSER, Menahem

Inventor： SHLICK, Mark ,  MURIN, Mark ,  LASSER, Menahem

IPC: G06F11/10

CPC classification number: G06F11/1064

Abstract: A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided.

Abstract translation: 一种在闪速存储器系统中存储和检索数据的方法，所述闪速存储器系统包括相对较高可靠性的高速缓存存储区域和相对较低可靠性的主存储区域，所述方法包括向数据添加纠错冗余级别 高于高速缓存存储区域所需的预定余量，将数据写入高速缓存存储区域，并从高速缓存存储区域直接复制到主存储区域，预定余量允许后续纠错 以补偿从高速缓存存储区域和主存储区域累积的错误。 以这种方式，可以使用存储器管芯复制操作将数据从高速缓存复制到主存储器，并且避免通过数据总线向闪存控制器传输四次。

公开(公告)号：WO2008004216A3

公开(公告)日：2009-04-30

申请号：PCT/IL2007000814

申请日：2007-07-01

Applicant: SANDISK IL LTD ,  MURIN MARK

Inventor： MURIN MARK

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C8/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A multi-bit-per-cell flash memory device supports a command such that each invocation of the command by the device's host changes respective values of one or more types of reference voltage (e.g., all read reference voltages and/or all program verify reference voltages) of the device to respective new values.

Abstract translation: 多单元闪存设备支持命令，使得设备主机对命令的每次调用改变一种或多种类型的参考电压的相应值（例如，所有读取的参考电压和/或所有程序验证参考 电压）到相应的新值。

公开(公告)号：WO2007043042A3

公开(公告)日：2008-12-31

申请号：PCT/IL2006001159

申请日：2006-10-04

Applicant: UNIV RAMOT ,  LITSYN SIMON ,  ALROD IDAN ,  SHARON ERAN ,  MURIN MARK ,  LASSER MENACHEM

Inventor： LITSYN SIMON ,  ALROD IDAN ,  SHARON ERAN ,  MURIN MARK ,  LASSER MENACHEM

IPC: G11C29/00

CPC classification number: G06F11/1072

Abstract: A plurality of logical pages is stored in a MBC flash memory (42) along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory (42), the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices (54, 56, 5S), the controllers of such memory devices (54, 56, 58), and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract translation: 多个逻辑页面与相应的ECC位一起存储在MBC闪速存储器（42）中，其中至少一个MBC单元存储来自多于一个逻辑页面的位，并且至少一个ECC位应用于两个 或更多的逻辑页面。 当从存储器（42）读取页面时，读取的数据位使用被读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储设备（54,56,5S），这些存储设备（54,56,58）的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：WO2008132725A4

公开(公告)日：2008-11-06

申请号：PCT/IL2008/000531

申请日：2008-04-17

Applicant: SANDISK IL LTD. ,  LASSER, Menahem ,  MURIN, Mark

Inventor： LASSER, Menahem ,  MURIN, Mark

IPC: G06F12/02

Abstract: User data are stored in a memory that includes one or more blocks of pages by, for one of the blocks, and optionally for all of the blocks, whenever writing any of the user data to that block, writing the block according to a predefined plan for specifying, with respect to each page of that block, a portion of the user data that is to be written to that page. Alternatively or additionally, each page that stores user data has associated therewith a metadatum related to the age of the user data stored therein; and, for one of the blocks, at any time that two or more of the pages of that block store user data, a common value of the metadatum is associated with all such pages.

公开(公告)号：WO2007083303A2

公开(公告)日：2007-07-26

申请号：PCT/IL2007000061

申请日：2007-01-17

Applicant: SANDISK IL LTD ,  MURIN MARK

Inventor： MURIN MARK

IPC: H03M13/00

CPC classification number: G11C11/5621 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00

Abstract: A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.

Abstract translation: 存储数据的方法包括：将具有第一误差概率的非易失性存储器的位位置中的数据的第一部分存储; 将所述数据的第二部分存储在具有第二误差概率的所述非易失性存储器的比特位置中，其中所述第二误差概率低于所述第一误差概率; 存储纠错奇偶校验位与数据; 以及使用纠错奇偶校验位来应用纠错方案来读取数据，其中在检查所述第二部分的任何位之前检查所述第一部分的至少一位以进行校正。 在检查所有数据的校正之前，停止纠错方案。

公开(公告)号：WO2007049272A2

公开(公告)日：2007-05-03

申请号：PCT/IL2006/001220

申请日：2006-10-24

Applicant: MSYSTEMS LTD. ,  LASSER, Menachem ,  MURIN, Mark

Inventor： LASSER, Menachem ,  MURIN, Mark

IPC: G06F11/07

CPC classification number: G06F11/1072 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/28

Abstract: Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages. Alternatively or additionally, these modified reference voltages may be determined as needed, for example, using randomly generated values or in accordance with information provided by the error detection and correction module. Methods, devices and computer readable code for reading data for situations where there is no error correction failure are also provided.

Abstract translation: 公开了用于从一个或多个闪存单元读取数据以及从读取错误中恢复的方法，设备和计算机可读代码。 在一些实施例中，在通过错误检测和校正模块进行纠错故障的情况下，例如，可以使用一个或多个修改的参考电压重新读取闪存单元至少一次，直到可以承载成功的纠错 出。 在一些实施例中，在成功的纠错之后，处理随后的读取请求，而不会在此期间将数据（例如，读取数据的可靠值）重新写入闪速存储器单元。 在一些实施例中，与校正错误相关联的读数的参考电压可以存储在存储器中，并在响应随后的读取请求时被检索。 在一些实施例中，修改的参考电压是预定的参考电压。 或者或另外，这些修改的参考电压可以根据需要例如使用随机生成的值或根据由错误检测和校正模块提供的信息来确定。 还提供了用于在没有错误校正失败的情况下读取数据的方法，设备和计算机可读代码。