公开(公告)号：WO2004093090A1

公开(公告)日：2004-10-28

申请号：PCT/US2004/010991

申请日：2004-04-08

Applicant: SANDISK CORPORATION ,  CHEN, Jian ,  QUADER, Khandker, N.

Inventor： CHEN, Jian ,  QUADER, Khandker, N.

IPC: G11C11/56

CPC classification number: G11C7/04 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

Abstract: In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

Abstract translation: 在非易失性存储器中，用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿，而不是硬连线到地。 在示例性实施例中，用于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。 根据另一方面，提出了可以利用操作条件补偿的感测参数的擦除过程。 由于感测参数不再固定为对应于0伏的值，而是根据工作条件进行移位，即使在降低的工作电压下，也为各种擦除验证电平提供足够的余量。

公开(公告)号：WO2005031754A1

公开(公告)日：2005-04-07

申请号：PCT/JP2004/012419

申请日：2004-08-23

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SanDisk Corporation ,  TANAKA, Tomoharu ,  KAWAI, Koichi ,  QUADER, Khandker, N.

Inventor： TANAKA, Tomoharu ,  KAWAI, Koichi ,  QUADER, Khandker, N.

IPC: G11C16/22

CPC classification number: G11C16/22

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract translation: 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。

公开(公告)号：WO2003105155A1

公开(公告)日：2003-12-18

申请号：PCT/US2003/005354

申请日：2003-02-20

Applicant: SANDISK CORPORATION ,  MAK, Alexander, K. ,  PHAM, Long, C. ,  GROSS, Stephen, J. ,  TUERS, Edward, P. ,  QUADER, Khandker, N.

Inventor： MAK, Alexander, K. ,  PHAM, Long, C. ,  GROSS, Stephen, J. ,  TUERS, Edward, P. ,  QUADER, Khandker, N.

IPC: G11C7/10

CPC classification number: G11C7/1057 ,  G11C7/1024 ,  G11C7/1051 ,  G11C16/26

Abstract: Methods and apparatus for reducing read access times associated with obtaining stored data from a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for providing data to a bus within a memory system that includes a storage area involves providing a first signal (REM) within the memory system and enabling an output buffer in response to the first signal. The first signal indicates that the data is to be provided to the bus from the storage area, and is of a first level which has a first duration. The output buffer provides the data from the storage area to the bus, and remains substantially enabled while the first signal is of the first level. In one embodiment, the method also includes providing a second signal (OE) as an input to the output buffer to enable the output buffer.

Abstract translation: 公开了用于减少与从非易失性存储器系统获得存储的数据相关联的读访问时间的方法和装置。 根据本发明的一个方面，一种用于向包括存储区域的存储器系统内的总线提供数据的方法包括在存储器系统内提供第一信号（REM），并响应于第一信号启用输出缓冲器。 第一信号指示数据将从存储区域提供给总线，并且是具有第一持续时间的第一级。 输出缓冲器将数据从存储区域提供给总线，并且在第一信号处于第一级时保持基本使能。 在一个实施例中，该方法还包括提供第二信号（OE）作为输出到输出缓冲器以启用输出缓冲器。

公开(公告)号：WO2005031753A1

公开(公告)日：2005-04-07

申请号：PCT/US2004/031082

申请日：2004-09-21

Applicant: SANDISK CORPORATION ,  QUADER, Khandker, N. ,  CERNEA, Raul-Adrian

Inventor： QUADER, Khandker, N. ,  CERNEA, Raul-Adrian

IPC: G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3418

Abstract: The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.

Abstract translation: 本发明提供一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。 对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。 所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。 根据本发明的另一方面，这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外周边区域的情况下实现。 优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。

公开(公告)号：WO2005031751A1

公开(公告)日：2005-04-07

申请号：PCT/JP2004/012420

申请日：2004-08-23

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SanDisk Corporation ,  NAGASHIMA, Hiroyuki ,  TANAKA, Tomoharu ,  KAWAI, Koichi ,  QUADER, Khandker, N.

Inventor： NAGASHIMA, Hiroyuki ,  TANAKA, Tomoharu ,  KAWAI, Koichi ,  QUADER, Khandker, N.

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C2211/5641

Abstract: A nonvolatile semiconductor memory device includes a memory cell array, interface, and write circuit. The write circuit can selectively write data in the memory cell array by first write procedures or second write procedures in accordance with a data write command input to the interface. When a data write command by the first write procedures is input from the interface, the write circuit executes the command when flag data has a first value and does not execute the command when the flag data has a second value.

Abstract translation: 非易失性半导体存储器件包括存储单元阵列，接口和写入电路。 写入电路可以根据输入到接口的数据写入命令，通过第一写入过程或第二写入过程来选择性地将数据写入存储单元阵列。 当从接口输入通过第一写入过程的数据写入命令时，当标志数据具有第一值时，写入电路执行命令，并且当标志数据具有第二值时不执行命令。