Abstract:
A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.
Abstract:
A method and an apparatus for estimating a location of a terminal are provided. The method includes: receiving at least one base station signal from each of at least one base station; computing received signal information with respect to the received signal; and estimating the location of the terminal based on signal transmission direction information associated with the base station and the computed received signal information. The present invention can accurately estimate the location of the terminal based on directional information of base station signals.
Abstract:
A method for fabricating an integrated circuit having at least one integrated circuit component (14) fabricated in a silicon substrate (12) and a second device (30) that is to be fabricated on a silicon oxide layer (16) that covers the integrated circuit component (14). The integrated circuit component (14) has a terminal that is to be connected to a corresponding terminal on the second device (30). The second device (30) includes an electrode structure (35) in contact with a dielectric component that includes a layer (33) of ferroelectric material. In the method of the present invention, a boundary layer comprising non-conducting polysilicon (17) is deposited over the silicon oxide layer (16). The electrode structure (35) is then fabricated by depositing one or more layers over the boundary layer (17). The ferroelectric layer (33) is then deposited over the electrode structure (35) and etched to provide the dielectric component. The boundary layer is then removed utilizing an etchant that etches silicon oxide much slower than polysilicon.
Abstract:
A method for connecting a silicon substrate to an electrical component via a platinum conductor. A capacitor (40) can be built over the source (34) of a transistor (32). Cell (30) is constructed by first constructing a CMOS transistor (32) having a drain (33), gate region consisting of gate oxide (35) and gate electrode (36), and source (34). The gate structures are insulated with a glass layer (37). A capacitor (40) is then constructed by depositing a bottom electrode (42) on source (34). A ceramic layer (43) is then deposited and sintered. Finally, the top electrode (41) is deposited. The resulting structure may be heated in the presence of oxygen to a temperature in excess of 800 DEG C without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.
Abstract:
A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.
Abstract:
A method of determining a location of a mobile communication terminal, including: receiving base station signal information from the mobile communication terminal, the base station signal information being transmitted from a plurality of base stations including a reference base station to the mobile communication terminal; selecting neighboring base stations, which are located within a predetermined distance from the reference base station, from base stations corresponding to the base station signal information by searching a network database; determining whether the base station signal information corresponding to the neighboring base stations and the reference base station is received via a repeater; determining a vector proceeding order with respect to the reference base station and the neighboring base stations; setting a vector proceeding point, depending upon the determination on whether the base station signal information corresponding to the neighboring base stations and the reference base station is received via the repeater; setting a location mode of the mobile communication terminal according to a domination degree of the reference base station with respect to the mobile communication terminal; determining the location of the mobile communication terminal by determining a vector-based location with respect to the vector proceeding point according to the vector proceeding order, using a PN strength of the base station signal information according to the location mode.
Abstract:
A ferroelectric memory cell (200) for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer (213) by setting the direction of the remnant polarization. The ferroelectric memory cell is designed to store the information at a temperature less than a first temperature. The memory cell includes top and bottom contacts that sandwich the dielectric layer (213) which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 °C. The dielectric layer (213) is encapsulated in an oxygen impermeable material such that the encapsulating layer (221) prevents oxygen from entering or leaving the dielectric layer (213). The memory also includes a hydrogen barrier layer (225) that inhibits the flow of oxygen to the top and bottom electrodes when the memory cell is placed in a gaseous environment containing hydrogen. In one embodiment of the invention, a hydrogen absorbing layer is included. In the preferred embodiment of the present invention, the hydrogen barrier layer (225) is constructed from a material that will also bind hydrogen ions.
Abstract:
A high density non volatile ferroelectric-based memory (500) based on ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET (10). A memory using either the one or two bit storage cells includes a plurality of word storage cells (502) organized into a rectangular array including a plurality of columns and rows. Each of the single bit memory cells (101) includes a pass transistor (115) and a ferroelectric storage element (116). All of the gates of the ferroelectric storage elements transistors are connected to a common gate electrode (122), and all of the source electrodes are connected to a common source electrode (121). If the memory is built as a two bit storage cell (300), all of the common source electrodes in each of the columns are connected electrically to a column electrode (504) corresponding to that column and all of the pass gates in each of the rows that are connected electrically to a row electrode (503) corresponding to that row.
Abstract:
An improved ferroelectric FET structure (10) in which the ferroelectric layer (14) is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer (16) having first and second contacts (18, 19) thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode (12) and a ferroelectric layer (14) which is sandwiched between the semiconductor layer (16) and the bottom electrode (12). The ferroelectric layer (14) is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentration between 1 % and 8 %.
Abstract:
A shipping container system comprises an inner liner (1) for insertion into an inner shipping container (15), for insertion into an outer shipping container (16). The inner liner (1) comprises a layer of single- or double-bubble radiant barrier material (13) within a sealed vinyl pouch (21). Between the outer container (6) and the inner container (5) there is furnished at least one spacer tray (3), for providing a partially-surrounding pocket of air in contact with the exterior surface of the inner container (5). During sealing of the pouch (21), a pocket of air is allowed to remain in its interior so that the radiant barrier material (13) floats within the sealed pouch (21). The pockets of air provided allow for maximization of the thermal insulating properties of the system due primarily to the thermal reflective property of the radiant barrier material. The vinyl construction of the pouch material provides a durable protective cover for the radiant barrier material.