公开(公告)号：WO2008009929A2

公开(公告)日：2008-01-24

申请号：PCT/GB2007/002710

申请日：2007-07-18

Applicant: PLASTIC LOGIC LIMITED ,  REYNOLDS, Kieran ,  REEVES, William

Inventor： REYNOLDS, Kieran ,  REEVES, William

IPC: H01L51/52 ,  H01L27/32

CPC classification number: H05B33/04 ,  H01L23/10 ,  H01L27/3244 ,  H01L51/5246 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of processing a flexible encapsulation scheme to encapsulate a flexible device, such as a display device in order to provide structural support for the display module. An upper transparent encapsulation layer covers and protects the media and active area of the device. A lower encapsulation layer is deposited over the under side of the display to complete the encapsulation and the two protective encapsulation layers are sealed. A driver housing may be positioned at the opposite end of the device to the overlap region of the encapsulation layers in order to protect the driver electronics.

Abstract translation: 一种处理柔性封装方案以封装诸如显示装置的柔性装置以便为显示模块提供结构支撑的方法。 上透明封装层覆盖并保护设备的介质和有效区域。 下封装层沉积在显示器的下侧以完成封装，并且两个保护性封装层被密封。 为了保护驱动器电子装置，驱动器外壳可以位于装置的相对端处于封装层的重叠区域。

公开(公告)号：WO2006106365A2

公开(公告)日：2006-10-12

申请号：PCT/GB2006/050078

申请日：2006-04-05

Applicant: Plastic Logic Limited ,  REYNOLDS, Kieran ,  RAMSDALE, Catherine ,  JACOBS, Kevin ,  REEVES, William

Inventor： REYNOLDS, Kieran ,  RAMSDALE, Catherine ,  JACOBS, Kevin ,  REEVES, William

IPC: H01L51/00

CPC classification number: G02F1/1368 ,  G02F1/133305 ,  G02F1/136213 ,  G02F1/167 ,  H01L27/283 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3274 ,  H01L51/0003 ,  H01L51/10 ,  H01L51/56

Abstract: The present invention relates to a multiple layer pixel architecture for an active matrix display in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the TFTs are formed. A multilayer electronic structure adapted to solution deposition, the structure including a thin film transistor (TFT) for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure comprises a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.

Abstract translation: 本发明涉及一种用于有源矩阵显示器的多层像素架构，其中在与形成TFT的栅电极的金属层上分离的金属层上形成公共总线。 一种适于溶液沉积的多层电子结构，所述结构包括用于驱动有源矩阵光电子器件的像素的薄膜晶体管（TFT）和用于存储电荷以维持所述有源矩阵像素的电状态的电容器，其中所述结构包括 至少四个由至少三个电介质层隔开的导电层的衬底，所述导电层中的第一和第二导电层分别限定漏极/源电极和所述晶体管的栅电极，第三和第四导电层限定相应的第一 和所述电容器的第二板，并且其中所述电容器和所述晶体管被横向定位成使得它们在垂直方向上重叠。

公开(公告)号：WO03041184A3

公开(公告)日：2003-10-16

申请号：PCT/GB0205054

申请日：2002-11-07

Applicant: UNIV CAMBRIDGE TECH ,  FREY GITTI ,  REYNOLDS KIERAN JOHN ,  SIRRINGHAUS HENNING ,  FRIEND RICHARD HENRY

Inventor： FREY GITTI ,  REYNOLDS KIERAN JOHN ,  SIRRINGHAUS HENNING ,  FRIEND RICHARD HENRY

IPC: H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L51/20

CPC classification number: H01L51/0516 ,  H01L51/0021 ,  H01L51/0036 ,  H01L51/0039 ,  H01L51/0043 ,  H01L51/0541 ,  H01L51/0545

Abstract: A field effect transistor is provided which comprises a gate electrode, a source electrode, a drain electrode, at least one organic semiconducting layer, and a hole transport layer for transferring holes from said source and drain electrodes to said organic semiconducting layer, wherein said hole transport layer comprises a layered metal chalcogenide. Processes for depositing a thin layer of a layered metal dichalcogenide on a substrate and for producing top gate structures on a layered metal chalcogenide layer in the manufacture of field effect transistors according to the invention are also provided.

Abstract translation: 提供了一种场效应晶体管，其包括栅电极，源电极，漏电极，至少一个有机半导体层以及用于将空穴从所述源电极和漏电极转移到所述有机半导体层的空穴传输层，其中所述孔 传输层包含层状金属硫族化合物。 还提供了在制造根据本发明的场效应晶体管时在基底上沉积层状金属硫族化合物薄层并在层状金属硫族化物层上制造顶栅结构的方法。

公开(公告)号：WO2003041183A1

公开(公告)日：2003-05-15

申请号：PCT/GB2002/004988

申请日：2002-11-06

Applicant: CAMBRIDGE UNIVERSITY TECHNICAL SERVICES LIMITED ,  FREY, Gitti ,  REYNOLDS, Kieran, John

Inventor： FREY, Gitti ,  REYNOLDS, Kieran, John

IPC: H01L51/20

CPC classification number: H01L51/0077 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0039 ,  H01L51/0043 ,  H01L51/0044 ,  H01L51/0059 ,  H01L51/5096 ,  H01L51/5206

Abstract: An electroluminescent device is provided which comprises a hole injecting electrode, an electron injecting electrode and at least one organic light emitting layer disposed between said hole injecting electrode and said electron injecting electrode, wherein said hole injecting electrode is a layered metal chalcogenide. Layered metal chalcogenides are particularly suitable for use as a hole injecting layer as they high work functions, allow easy chemical (solution) processing, form continues ultra thin films, allow simple conversion into the corresponding insulating oxide and are stable at high temperatures. A process for depositing a thin layer of a layered metal dichalcogenide on a substrate in the manufacture of electroluminescent devices of the invention is also provided.

Abstract translation: 提供了一种电致发光器件，其包括空穴注入电极，电子注入电极和设置在所述空穴注入电极和所述电子注入电极之间的至少一个有机发光层，其中所述空穴注入电极是层状金属硫族化物。 层状金属硫族化物特别适合用作空穴注入层，因为它们具有高功函数，易于化学（溶液）处理，形成继续的超薄膜，允许简单转换成相应的绝缘氧化物，并在高温下稳定。 还提供了在本发明的电致发光器件的制造中在基板上沉积层状金属二硫属元素的薄层的工艺。

公开(公告)号：WO2002095841A2

公开(公告)日：2002-11-28

申请号：PCT/GB2002/002306

申请日：2002-05-16

Applicant: CAMBRIDGE UNIVERSITY TECHNICAL SERVICES LIMITED ,  FREY, Gitti ,  REYNOLDS, Kieran, John

Inventor： FREY, Gitti ,  REYNOLDS, Kieran, John

IPC: H01L51/20

CPC classification number: H01L51/5206 ,  H01L51/5088 ,  Y10S428/917

Abstract: An electroluminescent device comprises a hole injecting electrode (2), an electron injecting electrode (5, 69 and at least one organic light emitting layer (4) disposed between said hole injecting electrode (2) and said electron injecting electrode (5, 6) wherein a layered metal chalcogenide layer (3) is disposed between said hole injecting electrode and said light emitting layer.

Abstract translation: 电致发光器件包括空穴注入电极（2），设置在所述空穴注入电极（2）和所述电子注入电极（5,6）之间的电子注入电极（5,69和至少一个有机发光层） 其中层间金属硫族化物层（3）设置在所述空穴注入电极和所述发光层之间。

公开(公告)号：WO2009133388A1

公开(公告)日：2009-11-05

申请号：PCT/GB2009/050423

申请日：2009-04-27

Applicant: PLASTIC LOGIC LIMITED ,  VON WERNE, Tim ,  REYNOLDS, Kieran ,  PUI, Boon, Hean

Inventor： VON WERNE, Tim ,  REYNOLDS, Kieran ,  PUI, Boon, Hean

IPC: H01L27/32

CPC classification number: H01L27/3265 ,  H01L27/283 ,  H01L2251/5338

Abstract: The present invention relates to a semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighbouring device. Such a configuration allows for improved device performance, resulting from features such as a greater storage capacitance.

Abstract translation: 本发明涉及一种半导体器件结构，其中顶部像素电极以偏置配置沉积，例如与COM电极重叠，以及相邻器件的栅极电极。 这样的配置允许由诸如更大存储电容的特征导致的改进的器件性能。

公开(公告)号：WO02095841A3

公开(公告)日：2003-03-06

申请号：PCT/GB0202306

申请日：2002-05-16

Applicant: UNIV CAMBRIDGE TECH ,  FREY GITTI ,  REYNOLDS KIERAN JOHN

Inventor： FREY GITTI ,  REYNOLDS KIERAN JOHN

IPC: H05B33/22 ,  C09K11/06 ,  H01L51/50 ,  H05B33/26 ,  H01L51/20

CPC classification number: H01L51/5206 ,  H01L51/5088 ,  Y10S428/917

Abstract: An electroluminescent device comprises a hole injecting electrode (2), an electron injecting electrode (5, 69 and at least one organic light emitting layer (4) disposed between said hole injecting electrode (2) and said electron injecting electrode (5, 6) wherein a layered metal chalcogenide layer (3) is disposed between said hole injecting electrode and said light emitting layer.

Abstract translation: 电致发光器件包括空穴注入电极（2），设置在所述空穴注入电极（2）和所述电子注入电极（5,6）之间的电子注入电极（5,69和至少一个有机发光层） 其中层间金属硫族化物层（3）设置在所述空穴注入电极和所述发光层之间。

公开(公告)号：WO2003041184A2

公开(公告)日：2003-05-15

申请号：PCT/GB2002/005054

申请日：2002-11-07

Applicant: CAMBRIDGE UNIVERSITY TECHNICAL SERVICES LIMITED ,  FREY, Gitti ,  REYNOLDS, Kieran, John ,  SIRRINGHAUS, Henning ,  FRIEND, Richard, Henry

Inventor： FREY, Gitti ,  REYNOLDS, Kieran, John ,  SIRRINGHAUS, Henning ,  FRIEND, Richard, Henry

IPC: H01L51/20

CPC classification number: H01L51/0516 ,  H01L51/0021 ,  H01L51/0036 ,  H01L51/0039 ,  H01L51/0043 ,  H01L51/0541 ,  H01L51/0545

Abstract: A field effect transistor is provided which comprises a gate electrode, a source electrode, a drain electrode, at least one organic semiconducting layer, and a hole transport layer for transferring holes from said source and drain electrodes to said organic semiconducting layer, wherein said hole transport layer comprises a layered metal chalcogenide. Processes for depositing a thin layer of a layered metal dichalcogenide on a substrate and for producing top gate structures on a layered metal chalcogenide layer in the manufacture of field effect transistors according to the invention are also provided.

Abstract translation: 提供一种场效应晶体管，其包括栅电极，源电极，漏电极，至少一个有机半导体层和用于将空穴从所述源电极和漏电极传送到所述有机半导体层的空穴传输层，其中所述孔 传输层包括层状金属硫族化物。 还提供了在根据本发明的场效应晶体管的制造中，在层叠的金属硫族化物层上沉积层状金属二硫属元素的薄层并在基板上形成顶栅结构的工艺。

公开(公告)号：WO2006106365A3

公开(公告)日：2008-12-11

申请号：PCT/GB2006050078

申请日：2006-04-05

Applicant: PLASTIC LOGIC LTD ,  REYNOLDS KIERAN ,  RAMSDALE CATHERINE ,  JACOBS KEVIN ,  REEVES WILLIAM

Inventor： REYNOLDS KIERAN ,  RAMSDALE CATHERINE ,  JACOBS KEVIN ,  REEVES WILLIAM

IPC: H01L27/32

CPC classification number: G02F1/1368 ,  G02F1/133305 ,  G02F1/136213 ,  G02F1/167 ,  H01L27/283 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3274 ,  H01L51/0003 ,  H01L51/10 ,  H01L51/56

Abstract: The present invention relates to a multiple layer pixel architecture for an active matrix display in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the TFTs are formed. A multilayer electronic structure adapted to solution deposition, the structure including a thin film transistor (TFT) for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure comprises a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.

Abstract translation: 本发明涉及一种用于有源矩阵显示器的多层像素架构，其中在与形成TFT的栅电极的金属层上分离的金属层上形成公共总线。 一种适于溶液沉积的多层电子结构，所述结构包括用于驱动有源矩阵光电子器件的像素的薄膜晶体管（TFT）和用于存储电荷以维持所述有源矩阵像素的电状态的电容器，其中所述结构包括 至少四个由至少三个电介质层隔开的导电层的衬底，所述导电层中的第一和第二导电层分别限定漏极/源电极和所述晶体管的栅电极，第三和第四导电层限定相应的第一 和所述电容器的第二板，并且其中所述电容器和所述晶体管被横向定位成使得它们在垂直方向上重叠。

公开(公告)号：WO2011151456A1

公开(公告)日：2011-12-08

申请号：PCT/EP2011/059219

申请日：2011-06-03

Applicant: Plastic Logic Limited ,  REYNOLDS, Kieran ,  JOIMEL, Jerome

Inventor： REYNOLDS, Kieran ,  JOIMEL, Jerome

IPC: H01L29/786 ,  H01L21/77 ,  H01L51/00

CPC classification number: H01L21/56 ,  H01L24/80 ,  H01L27/1266 ,  H01L29/78603 ,  H01L51/003 ,  H01L51/0097

Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.

Abstract translation: 一种技术，包括：将装置基板安装在处理支架上，在装置基板上形成一个或多个电子元件，并将装置基板安装在处理支架上; 其中所述器件衬底包括有机支撑结构，并且为所述上覆的电子元件提供初级保护，以抵抗来自与所述一个或多个电子元件相对的器件衬底的一侧的退化物质的侵入。