公开(公告)号：WO2008058141A2

公开(公告)日：2008-05-15

申请号：PCT/US2007083809

申请日：2007-11-06

Applicant: ALTERA CORP ,  CHU MICHAEL H M ,  HUANG JOSEPH ,  SUNG CHIAKANG ,  CHONG YAN ,  BELLIS ANDREW ,  CLARKE PHILIP ,  ROGE MANOJ B

Inventor： CHU MICHAEL H M ,  HUANG JOSEPH ,  SUNG CHIAKANG ,  CHONG YAN ,  BELLIS ANDREW ,  CLARKE PHILIP ,  ROGE MANOJ B

IPC: G06F5/16

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract translation: 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

公开(公告)号：WO2008058141A3

公开(公告)日：2008-05-15

申请号：PCT/US2007/083809

申请日：2007-11-06

Applicant: ALTERA CORPORATION ,  CHU, Michael H. M. ,  HUANG, Joseph ,  SUNG, Chiakang ,  CHONG, Yan ,  BELLIS, Andrew ,  CLARKE, Philip ,  ROGE, Manoj B.

Inventor： CHU, Michael H. M. ,  HUANG, Joseph ,  SUNG, Chiakang ,  CHONG, Yan ,  BELLIS, Andrew ,  CLARKE, Philip ,  ROGE, Manoj B.

IPC: H03K19/173

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.