公开(公告)号：WO2011075540A3

公开(公告)日：2011-10-27

申请号：PCT/US2010060597

申请日：2010-12-15

Applicant: ALTERA CORP ,  NAGARAJAN PRADEEP ,  CHONG YAN ,  SUNG CHIAKANG ,  HUANG JOSEPH

Inventor： NAGARAJAN PRADEEP ,  CHONG YAN ,  SUNG CHIAKANG ,  HUANG JOSEPH

IPC: H03L7/081 ,  H03K5/13

CPC classification number: H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable and fixed delay blocks inverts a received signal to generate an inverted signal.

Abstract translation: 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。 可变和固定延迟块中的每一个反转接收信号以产生反相信号。

公开(公告)号：WO2008058141A3

公开(公告)日：2008-05-15

申请号：PCT/US2007/083809

申请日：2007-11-06

Applicant: ALTERA CORPORATION ,  CHU, Michael H. M. ,  HUANG, Joseph ,  SUNG, Chiakang ,  CHONG, Yan ,  BELLIS, Andrew ,  CLARKE, Philip ,  ROGE, Manoj B.

Inventor： CHU, Michael H. M. ,  HUANG, Joseph ,  SUNG, Chiakang ,  CHONG, Yan ,  BELLIS, Andrew ,  CLARKE, Philip ,  ROGE, Manoj B.

IPC: H03K19/173

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

公开(公告)号：WO2011091073A3

公开(公告)日：2011-11-17

申请号：PCT/US2011021762

申请日：2011-01-19

Applicant: ALTERA CORP ,  CHONG YAN ,  HUANG JOSEPH ,  NAGARAJAN PRADEEP ,  SUNG CHIAKANG

Inventor： CHONG YAN ,  HUANG JOSEPH ,  NAGARAJAN PRADEEP ,  SUNG CHIAKANG

IPC: G11C7/22 ,  G11C7/10

CPC classification number: H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

Abstract translation: 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 该IC包括分离器电路，其被耦合以接收时钟信号。 时钟信号被分成两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路被耦合到每个时钟信号。 每个延迟电路产生对应的时钟信号的延迟版本。 校正器电路被耦合以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

公开(公告)号：WO2008058141A2

公开(公告)日：2008-05-15

申请号：PCT/US2007083809

申请日：2007-11-06

Applicant: ALTERA CORP ,  CHU MICHAEL H M ,  HUANG JOSEPH ,  SUNG CHIAKANG ,  CHONG YAN ,  BELLIS ANDREW ,  CLARKE PHILIP ,  ROGE MANOJ B

Inventor： CHU MICHAEL H M ,  HUANG JOSEPH ,  SUNG CHIAKANG ,  CHONG YAN ,  BELLIS ANDREW ,  CLARKE PHILIP ,  ROGE MANOJ B

IPC: G06F5/16

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract translation: 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

公开(公告)号：WO2011091073A2

公开(公告)日：2011-07-28

申请号：PCT/US2011/021762

申请日：2011-01-19

Applicant: ALTERA CORPORATION ,  CHONG, Yan ,  HUANG, Joseph ,  NAGARAJAN, Pradeep ,  SUNG, Chiakang

Inventor： CHONG, Yan ,  HUANG, Joseph ,  NAGARAJAN, Pradeep ,  SUNG, Chiakang

IPC: G11C7/22 ,  G11C7/10

CPC classification number: H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

Abstract translation: 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

公开(公告)号：WO2011075540A2

公开(公告)日：2011-06-23

申请号：PCT/US2010/060597

申请日：2010-12-15

Applicant: ALTERA CORPORATION ,  NAGARAJAN, Pradeep ,  CHONG, Yan ,  SUNG, Chiakang ,  HUANG, Joseph

Inventor： NAGARAJAN, Pradeep ,  CHONG, Yan ,  SUNG, Chiakang ,  HUANG, Joseph

IPC: H03L7/081 ,  H03K5/13

CPC classification number: H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable and fixed delay blocks inverts a received signal to generate an inverted signal.

Abstract translation: 反馈回路电路包括相位检测器和延迟电路。 相位检测器基于延迟的周期性信号生成输出信号。 延迟电路耦合在延迟延迟链中，延迟延迟周期性信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以生成延迟输出信号。 延迟电路中的可变延迟块的延迟根据相位检测器的输出信号而变化。 每个延迟电路通过延迟路径中不同的延迟路径重新路由输入信号，以在反馈环电路的操作期间基于相位检测器的输出信号生成延迟的输出信号。 每个可变延迟块和固定延迟块反转接收到的信号以生成反相信号。