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    DYNAMIC MEMORY PERFORMANCE THROTTLING
    2.
    发明申请
    DYNAMIC MEMORY PERFORMANCE THROTTLING 审中-公开
    动态记忆性能曲线

    公开(公告)号：WO2013095675A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/067285

    申请日：2011-12-23

    Applicant: INTEL CORPORATION ,  TORONYI, Brian ,  SHOEMAKER, Kenneth

    Inventor： TORONYI, Brian ,  SHOEMAKER, Kenneth

    IPC: G11C11/4063 ,  G11C11/406 ,  G11C11/402 ,  G11C5/02

    CPC classification number: G06F12/00 ,  G06F13/1668 ,  G11C5/025 ,  G11C7/04 ,  G11C7/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254

    Abstract: Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements, the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misalignment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

    Abstract translation: 动态内存性能调节。 存储器件的实施例包括存储器堆叠，其包括耦合的存储器元件，存储器元件包括多个等级，多个等级包括第一等级和第二等级，以及包括存储器控制器的逻辑器件。 存储器控制器用于确定与第一等级的读请求相关的数据信号与第二等级的读请求之间的未对准量，并且在确定第一等级和第二等级之间的未对准大于阈值时 存储器控制器将在第一等级的数据信号和第二等级的数据信号之间插入时移。

    MEMORY OPERATIONS USING SYSTEM THERMAL SENSOR DATA
    4.
    发明申请
    MEMORY OPERATIONS USING SYSTEM THERMAL SENSOR DATA 审中-公开
    使用系统热传感器数据的存储器操作

    公开(公告)号：WO2013095674A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/067284

    申请日：2011-12-23

    Applicant: INTEL CORPORATION ,  SHOEMAKER, Kenneth ,  FAHEY, Paul

    Inventor： SHOEMAKER, Kenneth ,  FAHEY, Paul

    IPC: G11C5/02 ,  G11C7/04 ,  G11C11/406

    CPC classification number: G11C11/40626 ,  G06F1/206 ,  G11C5/025 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4067 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

    Abstract: Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

    Abstract translation: 使用系统热传感器数据进行存储操作。 存储器件的一个实施例包括存储器堆叠，其包括一个或多个耦合的存储器元件，以及与存储器堆叠耦合的逻辑芯片，逻辑芯片包括存储器控制器和一个或多个热传感器，其中一个或多个热传感器包括 位于逻辑芯片的第一区域中的第一热传感器。 存储器控制器获得一个或多个热传感器的热值，​​其中逻辑元件将使用热值来估计存储器堆的热条件，至少部分地基于对存储器堆的估计热条件的确定 第一热传感器位于逻辑元件的第一区域中。 至少部分地基于用于存储器堆栈的估计的热条件来修改存储器堆栈的一个或多个部分的刷新率。

    STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS
    5.
    发明申请
    STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS 审中-公开
    在设备互连中容纳变化的堆叠存储器

    公开(公告)号：WO2013081633A1

    公开(公告)日：2013-06-06

    申请号：PCT/US2011/063190

    申请日：2011-12-02

    Applicant: INTEL CORPORATION ,  SHOEMAKER, Kenneth ,  VOGT, Pete

    Inventor： SHOEMAKER, Kenneth ,  VOGT, Pete

    IPC: H01L27/10 ,  H01L27/108 ,  H01L21/8242

    CPC classification number: H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/18 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

    Abstract translation: 堆叠的存储器允许器件互连方面的差异。 存储器件的实施例包括用于存储器件的系统元件，所述系统元件包括多个焊盘，以及与所述系统元件连接的存储器堆栈，所述存储器堆栈具有一个或多个存储器管芯层，所述系统元件和 存储器堆叠包括用于连接第一存储器管芯层和系统元件的多个焊盘的互连。 对于存储器堆栈中的单个存储器管芯层，多个焊盘的第一子集用于用于系统元件和存储器堆叠的连接的第一组互连，并且对于两个或更多个存储器管芯层，第一组 子集和多个焊盘的另外的第二子集被用于第一组互连和用于系统元件和存储器堆的连接的第二组互连。

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