公开(公告)号：WO2013081572A3

公开(公告)日：2013-08-08

申请号：PCT/US2011054615

申请日：2011-10-03

Applicant: RAMBUS INC ,  ZERBE JARED ,  STONE TEVA ,  REN JIHONG

Inventor： ZERBE JARED ,  STONE TEVA ,  REN JIHONG

IPC: H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

公开(公告)号：WO2013081572A2

公开(公告)日：2013-06-06

申请号：PCT/US2011/054615

申请日：2011-10-03

Applicant: RAMBUS INC. ,  ZERBE, Jared ,  STONE, Teva ,  REN, Jihong

Inventor： ZERBE, Jared ,  STONE, Teva ,  REN, Jihong

IPC: H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统在时钟正向路径中包括连续时间线性均衡器。 可以调整均衡器以最小化时钟抖动，包括在启用时钟信号之后与前几个时钟沿相关的抖动。 减少早期抖动可以降低功率和电路的复杂性，否则需要快速开启系统。