公开(公告)号：WO2013081572A2

公开(公告)日：2013-06-06

申请号：PCT/US2011/054615

申请日：2011-10-03

Applicant: RAMBUS INC. ,  ZERBE, Jared ,  STONE, Teva ,  REN, Jihong

Inventor： ZERBE, Jared ,  STONE, Teva ,  REN, Jihong

IPC: H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统在时钟正向路径中包括连续时间线性均衡器。 可以调整均衡器以最小化时钟抖动，包括在启用时钟信号之后与前几个时钟沿相关的抖动。 减少早期抖动可以降低功率和电路的复杂性，否则需要快速开启系统。

公开(公告)号：WO2008085299A1

公开(公告)日：2008-07-17

申请号：PCT/US2007/025634

申请日：2007-12-13

Applicant: RAMBUS INC. ,  LIN, Qi ,  LEIBOWITZ, Brian ,  LEE, Hae-chang ,  REN, Jihong ,  OH, Kyung, Suk ,  ZERBE, Jared

Inventor： LIN, Qi ,  LEIBOWITZ, Brian ,  LEE, Hae-chang ,  REN, Jihong ,  OH, Kyung, Suk ,  ZERBE, Jared

IPC: H04L7/02 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter- symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 采样和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

公开(公告)号：WO2011008356A2

公开(公告)日：2011-01-20

申请号：PCT/US2010/036792

申请日：2010-05-31

Applicant: RAMBUS INC. ,  ZERBE, Jared ,  BATRA, Pradeep ,  LEIBOWITZ, Brian

Inventor： ZERBE, Jared ,  BATRA, Pradeep ,  LEIBOWITZ, Brian

IPC: H03K19/0175 ,  H04L25/02 ,  H03K5/1252

CPC classification number: H04L25/0264 ,  G06F1/10 ,  H03K5/1252

Abstract: A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.

Abstract translation: 第一集成电路（IC）具有可调延迟电路和第一接口电路。 向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。 第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。 电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。 可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。 在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。 在其他实施例中，电源电压用于在多个IC上产生时钟信号。

公开(公告)号：WO2011041060A2

公开(公告)日：2011-04-07

申请号：PCT/US2010/047282

申请日：2010-08-31

Applicant: RAMBUS INC. ,  SATARZADEH, Patrick ,  ZERBE, Jared ,  DALY, Barry

Inventor： SATARZADEH, Patrick ,  ZERBE, Jared ,  DALY, Barry

IPC: H03K5/13 ,  H03H11/26

CPC classification number: H03H11/265 ,  H03K5/131

Abstract: Described are integrated-circuit delay lines that include regulated and unregulated delay elements connected in series. The regulated delay elements exhibit relatively long delays that are stable over process, voltage, and temperature. The unregulated delay elements exhibit relatively short delays with fine adjustment granularity. A multiplexer selects various numbers of the delay elements to provide a range of delay settings. The multiplexer includes a number of smaller multiplexers cascaded to minimize the lead-in delay of the delay element. The delay elements and multiplexer can be single-ended or complementary.

Abstract translation: 描述的是集成电路延迟线，其包括串联连接的调节和非调节延迟元件。 稳定的延迟元件表现出相对较长的延迟，其在过程，电压和温度上是稳定的。 未调节的延迟元件表现出相对短的延迟，具有精细的调整粒度。 多路复用器选择各种数量的延迟元件以提供一定范围的延迟设置。 多路复用器包括多个较小的多路复用器级联以最小化延迟元件的导入延迟。 延迟元件和复用器可以是单端或互补的。

公开(公告)号：WO2008150321A1

公开(公告)日：2008-12-11

申请号：PCT/US2008/003961

申请日：2008-03-25

Applicant: RAMBUS INC. ,  KIM, Jaeha ,  LEE, Haechang ,  CHUN, Jung-Hoon ,  ZERBE, Jared

Inventor： KIM, Jaeha ,  LEE, Haechang ,  CHUN, Jung-Hoon ,  ZERBE, Jared

IPC: H04L5/04 ,  H04L25/03

CPC classification number: H04L25/03343 ,  H04B1/126 ,  H04L5/04 ,  H04L2025/03356 ,  H04L2025/03477 ,  H04L2025/03802

Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits (105,110) in the same direction over a single link (115). An equalizing transmitter (117) applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel (115). The transmitter modulates (133) at least one of the filter coefficients (155) with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver (120) ignores the apparent ISI to recover the main data, while an auxiliary receiver (135) detects (170) and demodulates (172) the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread- spectrum techniques to reduce the impact of the auxiliary data on the main data.

Abstract translation: 信号系统通过单个链路（115）在相同方向上支持集成电路（105,110）之间的主和辅助通信信道。 当通过通信信道（115）发送主数据时，均衡发射机（117）应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制（133）至少一个滤波器系数（155）以在所发送的信号中引起明显的ISI。 辅助接收机（135）检测（170）并解调（172）明显的ISI以恢复辅助数据，主接收机（120）忽略恢复主数据的明显ISI。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

公开(公告)号：WO2003032652A3

公开(公告)日：2003-04-17

申请号：PCT/US2002/032602

申请日：2002-10-11

Applicant: RAMBUS INC. ,  ZERBE, Jared ,  CHAU, Pak, Shing ,  STONECYPHER, William, Franklin

Inventor： ZERBE, Jared ,  CHAU, Pak, Shing ,  STONECYPHER, William, Franklin

IPC: G01R31/28

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit (101) circuit of the system and is transmitted to a receive (103) circuit. A similar pattern of information is generated in the receive (103) circuit and used as a reference. The receive (103) circuit compares the patterns. Any differences (114) between the patterns are observable. In one embodiment, a linear feedback shift (105, 108) register (LFSR) implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

公开(公告)号：WO2003032652A2

公开(公告)日：2003-04-17

申请号：PCT/US2002/032602

申请日：2002-10-11

Applicant: RAMBUS INC. ,  ZERBE, Jared ,  CHAU, Pak, Shing ,  STONECYPHER, William, Franklin

Inventor： ZERBE, Jared ,  CHAU, Pak, Shing ,  STONECYPHER, William, Franklin

IPC: H04Q

CPC classification number: G01R31/31717 ,  G01R31/31703 ,  G01R31/3183 ,  G06F11/221 ,  H04B3/32

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. Information obtained from testing may be used to assess the effects of various system parameters, including but not limited to output current, crosstalk cancellation coefficients, and self-equalization coefficients, and system parameters may be adjusted to optimize system performance. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract translation: 描述了用于评估和优化信令系统的方法和装置。 使用与信号系统的正常操作实际相关的相同电路进行评估。 提供了对信号系统的原位测试的能力，并且可以从系统中的接收电路的实际角度获得信息。 在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。 在接收电路中产生类似的信息模式并用作参考。 接收电路比较图案。 模式之间的任何差异是可观察的。 优选地，图案是允许执行许多测试迭代的重复图案。 在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。 从测试获得的信息可以用于评估各种系统参数的影响，包括但不限于输出电流，串扰消除系数和自平衡系数，并且可以调整系统参数以优化系统性能。 本发明的一个实施例可以用各种类型的信令系统来实现，包括具有单端信号和具有差分信号的信号系统。 本发明的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统和同时在单个导体上传送多个信息位的系统。

公开(公告)号：WO2009134844A1

公开(公告)日：2009-11-05

申请号：PCT/US2009/042044

申请日：2009-04-29

Applicant: RAMBUS INC. ,  ZERBE, Jared

Inventor： ZERBE, Jared

IPC: H04L7/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: H04L7/0008 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

Abstract: A system for communicating data between a first integrated circuit device and a second integrated circuit device. The first integrated circuit device transmits a timing signal to the second integrated circuit device, wherein the timing signal includes a first transition and a second transition. The first integrated circuit device then delays the data, so that the data is delayed relative to the timing signal by a first predetermined delay time. Next, the first integrated circuit device transmits the delayed data to the second integrated circuit device, which receives the timing signal and the delayed data. Next, the second integrated circuit device delays the first transition of the timing signal by a second predetermined delay time to generate a delayed version of the first transition. The second integrated circuit device then senses the data during a time interval between the delayed version of the first transition and the second transition.

Abstract translation: 一种用于在第一集成电路器件和第二集成电路器件之间传送数据的系统。 第一集成电路装置向第二集成电路装置发送定时信号，其中定时信号包括第一转换和第二转换。 第一集成电路装置然后延迟数据，使得数据相对于定时信号延迟第一预定延迟时间。 接下来，第一集成电路装置将延迟的数据发送到接收定时信号和延迟数据的第二集成电路装置。 接下来，第二集成电路装置将定时信号的第一次转换延迟第二预定延迟时间，以产生第一转换的延迟版本。 然后，第二集成电路装置在第一转变的延迟版本和第二转换之间的时间间隔期间感测数据。

公开(公告)号：WO2013085811A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/067277

申请日：2012-11-30

Applicant: RAMBUS INC.

Inventor： HOSSAIN, Masum ,  REN, Jihong ,  ZERBE, Jared ,  ARYANFAR, Farshid

IPC: H04L25/03 ,  H03M1/00

CPC classification number: G06F1/3203 ,  H04B1/12 ,  H04L7/0054 ,  H04L7/033 ,  H04L25/03006 ,  H04L25/03012 ,  H04L25/03057 ,  H04L25/03127 ,  H04L25/03146 ,  H04L25/03853 ,  H04L2025/03433

Abstract: A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI.

Abstract translation: 公开了一种接收机集成电路，其包括滤波器和线性均衡电路。 滤波器具有用于接收主要抽头和前置光标抽头的信号符号的输入，以减少作用在数据符号上的前标ISI。 线性均衡电路耦合到输出并与滤波器配合以进一步减少ISI。

公开(公告)号：WO2013085820A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/067401

申请日：2012-11-30

Applicant: RAMBUS INC.

Inventor： ZERBE, Jared ,  PATIL, Dinesh, Dilip

IPC: H04J14/02

CPC classification number: H04J14/0221 ,  H04B10/07955 ,  H04B10/67 ,  H04B10/69 ,  H04J14/02 ,  H04J14/0256

Abstract: A photonic communication system communicates M signals over a waveguide by modulating M wavelengths of light. N photonic rings at a receiver, where N is greater than M, are used to demodulate the M wavelengths. The modulated frequencies and resonant wavelengths of the receive rings are allowed to drift relative to one another. The number of receive rings is greater than the number of modulated frequency, and the number and optical characteristics of the receive rings are selected such that a subset of the receive rings effectively demodulates over the operational frequency range of the incoming light. The system tracks relative drift between the modulated wavelengths and the resonant wavelengths of the receiving rings and automatically selects the correct modulated signal or signals from among the receiving rings. The free spectral ranges and optical lengths of the receive rings are selected to reduce or minimize the number of receive rings required to span the optical bandwidth of the modulated light.

Abstract translation: 光子通信系统通过调制M个波长的波长在波导上传送M个信号。 N个大于M的接收机的N个光子环用于解调M个波长。 允许接收环的调制频率和谐振波长相对于彼此漂移。 接收环的数量大于调制频率的数量，并且选择接收环的数量和光学特性，使得接收环的子集在入射光的工作频率范围内有效地解调。 该系统跟踪调制波长和接收环谐振波长之间的相对漂移，并自动从接收环中选择正确的调制信号或信号。 选择接收环的自由频谱范围和光学长度以减少或最小化跨越调制光的光学带宽所需的接收环的数量。