公开(公告)号：WO2013137863A1

公开(公告)日：2013-09-19

申请号：PCT/US2012/028912

申请日：2012-03-13

Applicant: RAMBUS INC. ,  HOSSAIN, Masum ,  LEIBOWITZ, Brian ,  REN, Jihong

Inventor： HOSSAIN, Masum ,  LEIBOWITZ, Brian ,  REN, Jihong

IPC: H03L7/085 ,  H04L7/033

CPC classification number: H04L7/0016 ,  H03L7/1974 ,  H03L7/235 ,  H04L7/033 ,  H04L27/0014 ,  H04L27/32 ,  H04L2027/0016 ,  H04L2027/0036 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current- controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Abstract translation: 本公开提供了一种用于多车道通信系统的时钟恢复电路。 使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。 作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。 电压或电流控制延迟线也可用于相位调整全局恢复时钟，以减轻带限制，通道相关的高频抖动。

公开(公告)号：WO2008070138A2

公开(公告)日：2008-06-12

申请号：PCT/US2007/024948

申请日：2007-12-05

Applicant: RAMBUS INC. ,  ZERBE, Jared, L. ,  ASSADERAGHI, Fariborz ,  LEIBOWITZ, Brian, S. ,  LEE, Hae-chang ,  REN, Jihong ,  LIN, Qi

Inventor： ZERBE, Jared, L. ,  ASSADERAGHI, Fariborz ,  LEIBOWITZ, Brian, S. ,  LEE, Hae-chang ,  REN, Jihong ,  LIN, Qi

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

公开(公告)号：WO2008085299A1

公开(公告)日：2008-07-17

申请号：PCT/US2007/025634

申请日：2007-12-13

Applicant: RAMBUS INC. ,  LIN, Qi ,  LEIBOWITZ, Brian ,  LEE, Hae-chang ,  REN, Jihong ,  OH, Kyung, Suk ,  ZERBE, Jared

Inventor： LIN, Qi ,  LEIBOWITZ, Brian ,  LEE, Hae-chang ,  REN, Jihong ,  OH, Kyung, Suk ,  ZERBE, Jared

IPC: H04L7/02 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter- symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 采样和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

公开(公告)号：WO2013081572A3

公开(公告)日：2013-08-08

申请号：PCT/US2011054615

申请日：2011-10-03

Applicant: RAMBUS INC ,  ZERBE JARED ,  STONE TEVA ,  REN JIHONG

Inventor： ZERBE JARED ,  STONE TEVA ,  REN JIHONG

IPC: H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

公开(公告)号：WO2013028296A1

公开(公告)日：2013-02-28

申请号：PCT/US2012/047751

申请日：2012-07-20

Applicant: RAMBUS INC. ,  ARYANFAR, Farshid ,  REN, Jihong

Inventor： ARYANFAR, Farshid ,  REN, Jihong

IPC: H04B7/04 ,  H01Q3/26

CPC classification number: H01Q1/50 ,  H01Q1/241 ,  H01Q3/2647 ,  H01Q3/267 ,  H04B17/12 ,  H04B17/13 ,  H04B17/14

Abstract: The disclosed embodiments relate to a technique for calibrating a retro-directive array. During the calibration process, the system measures a gain g 1 through a first pair of antennas in the retro-directive array. Next, the system measures a gain g 2 through a second pair of antennas in the retro-directive array. The system then simultaneously measures a combined gain G 1 , 2 through the first and second pairs of antennas in the retro-directive array. If G 1 , 2 is less than g 1 + g 2 by more than a threshold value, the system calibrates a phase relationship between the first and second pairs of antennas.

Abstract translation: 所公开的实施例涉及用于校准后向指令阵列的技术。 在校准过程中，系统通过反向指令阵列中的第一对天线测量增益g1。 接下来，系统通过后向指令阵列中的第二对天线测量增益g2。 然后，该系统同时测量通过后向指令阵列中的第一和第二对天线的组合增益G1.2。 如果G1,2小于g1 + g2超过阈值，则系统校准第一和第二对天线之间的相位关系。

公开(公告)号：WO2009058790A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/081478

申请日：2008-10-28

Applicant: RAMBUS INC. ,  LIN, Qi ,  LEE, Hae-Chang ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

Inventor： LIN, Qi ,  LEE, Hae-Chang ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

IPC: H04L5/20

CPC classification number: H04L25/0272 ,  H04L5/20 ,  H04L25/0262

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,- the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract translation: 数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。 第一和第二相应的传输线包括数据接收器电路外部的一对传输线。 第一和第二接口从一对传输线接收传输信号。 共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。 差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。 所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。 差分模式电路与提取的时钟信号同步。

公开(公告)号：WO2009058789A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/081477

申请日：2008-10-28

Applicant: RAMBUS INC. ,  LIN, Qi ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

Inventor： LIN, Qi ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

IPC: H04L7/027 ,  H04L7/00

CPC classification number: H04L7/0008 ,  H04L7/065 ,  H04L25/0276 ,  H04L25/14

Abstract: A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

Abstract translation: 数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。 数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。 第一速率是第二速率的倍数，其中倍数大于1。 数据传输电路还包括与符号时钟同步的数据驱动器。 数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。 数据信号和时钟信号同时被驱动到一个或多个传输线上。

公开(公告)号：WO2009003129A3

公开(公告)日：2009-04-16

申请号：PCT/US2008068409

申请日：2008-06-26

Applicant: RAMBUS INC ,  LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

Inventor： LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

IPC: H04L25/02 ,  H04L1/20 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L1/203 ,  H04L1/205 ,  H04L25/0224 ,  H04L25/0242 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/03012 ,  H04L25/03343

Abstract: A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.

Abstract translation: 通信系统支持在相应的发送和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。 一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。 接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。 另一实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。 误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析位误差以测量通道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。 在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

公开(公告)号：WO2008063431A3

公开(公告)日：2008-11-13

申请号：PCT/US2007023600

申请日：2007-11-09

Applicant: RAMBUS INC ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  RATNAYAKE RUWAN

Inventor： LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  RATNAYAKE RUWAN

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A device (102) implements data reception with edge-based partial response decision feedback equalization. The device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data -signal (104). The tap weight adapter circuit (114) sets the tap weights based. on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal is generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Abstract translation: 设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。 该设备实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。 抽头重量适配器电路（114）基于抽头权重设置。 使用一组边缘采样器对先前确定的数据值和来自接收数据信号的边缘分析的输入。 边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。 时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。 边缘时钟信号是根据边缘采样器的信号和由均衡器确定的先前数据值产生的。

公开(公告)号：WO2013081572A2

公开(公告)日：2013-06-06

申请号：PCT/US2011/054615

申请日：2011-10-03

Applicant: RAMBUS INC. ,  ZERBE, Jared ,  STONE, Teva ,  REN, Jihong

Inventor： ZERBE, Jared ,  STONE, Teva ,  REN, Jihong

IPC: H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统在时钟正向路径中包括连续时间线性均衡器。 可以调整均衡器以最小化时钟抖动，包括在启用时钟信号之后与前几个时钟沿相关的抖动。 减少早期抖动可以降低功率和电路的复杂性，否则需要快速开启系统。