公开(公告)号：WO2013081572A3

公开(公告)日：2013-08-08

申请号：PCT/US2011054615

申请日：2011-10-03

Applicant: RAMBUS INC ,  ZERBE JARED ,  STONE TEVA ,  REN JIHONG

Inventor： ZERBE JARED ,  STONE TEVA ,  REN JIHONG

IPC: H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

公开(公告)号：WO2009003129A3

公开(公告)日：2009-04-16

申请号：PCT/US2008068409

申请日：2008-06-26

Applicant: RAMBUS INC ,  LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

Inventor： LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

IPC: H04L25/02 ,  H04L1/20 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L1/203 ,  H04L1/205 ,  H04L25/0224 ,  H04L25/0242 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/03012 ,  H04L25/03343

Abstract: A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.

Abstract translation: 通信系统支持在相应的发送和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。 一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。 接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。 另一实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。 误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析位误差以测量通道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。 在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

公开(公告)号：WO2008070138A9

公开(公告)日：2009-03-05

申请号：PCT/US2007024948

申请日：2007-12-05

Applicant: RAMBUS INC ,  ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

Inventor： ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).

Abstract translation: 收发机体系结构支持在高性能集成电路（IC）（105）和采用较不复杂的发射机和接收机（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信。 。 的。 通过在更高性能的通道侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路，体系结构补偿了通过双向lan进行通信的IC之间的性能不对称。 基于在更高性能IC（Rx1N）的接收机处的信号响应，高性能IC中的发射和接收均衡滤波器系数都可以自适应地更新（162）。

公开(公告)号：WO2008070138A3

公开(公告)日：2009-01-15

申请号：PCT/US2007024948

申请日：2007-12-05

Applicant: RAMBUS INC ,  ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

Inventor： ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).

Abstract translation: 收发器架构支持在高性能集成电路（IC）（105）和使用较不复杂的发送器和接收器（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信， 。 的。 架构通过在车道的较高性能侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路来补偿通过双向LAN通信的IC之间的性能不对称性。 基于在高性能IC（Rx1N）的接收机处的信号响应，可以自适应地更新（162）高性能IC中的发射和接收均衡滤波器系数。

公开(公告)号：WO2008063431A3

公开(公告)日：2008-11-13

申请号：PCT/US2007023600

申请日：2007-11-09

Applicant: RAMBUS INC ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  RATNAYAKE RUWAN

Inventor： LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  RATNAYAKE RUWAN

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A device (102) implements data reception with edge-based partial response decision feedback equalization. The device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data -signal (104). The tap weight adapter circuit (114) sets the tap weights based. on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal is generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Abstract translation: 设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。 该设备实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。 抽头重量适配器电路（114）基于抽头权重设置。 使用一组边缘采样器对先前确定的数据值和来自接收数据信号的边缘分析的输入。 边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。 时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。 边缘时钟信号是根据边缘采样器的信号和由均衡器确定的先前数据值产生的。