公开(公告)号：WO2007079206A2

公开(公告)日：2007-07-12

申请号：PCT/US2006/049531

申请日：2006-12-27

Applicant: SANDISK CORPORATION ,  HIGASHITANI, Masaaki ,  PHAM, Tuan ,  ICHIGE, Masayuki ,  HASHIMOTO, Koji ,  TANAKA, Satoshi ,  SUGIMAE, Kikuko

Inventor： HIGASHITANI, Masaaki ,  PHAM, Tuan ,  ICHIGE, Masayuki ,  HASHIMOTO, Koji ,  TANAKA, Satoshi ,  SUGIMAE, Kikuko

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques, hi one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3F or 5F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F5 and select gates of width 3F spaced apart by 3F or 5F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Abstract translation: 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择间隙，例如3F或5F。 第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F5的宽度为F的存储元件，并且通过3F或5F隔开的宽度3F的选择栅极。 在另一种方法中，将三个光掩模的图案转移到相应的光刻胶层以产生类似的最终结构。

公开(公告)号：WO2006112056A1

公开(公告)日：2006-10-26

申请号：PCT/JP2005/017206

申请日：2005-09-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SATO, Atsuhiro ,  SUGIMAE, Kikuko ,  ICHIGE, Masayuki

Inventor： SATO, Atsuhiro ,  SUGIMAE, Kikuko ,  ICHIGE, Masayuki

IPC: H01L27/115 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L27/11519 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

Abstract: A semiconductor integrated circuit device includes a cell well (CELL P-WELL), a memory cell array (3) formed on the cell well and having a memory cell area (11) and cell well contact area (13), first wiring bodies (BL) arranged in the memory cell area, and second wiring bodies (CPWELL) arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.

Abstract translation: 一种半导体集成电路器件包括一个单元阱（CELL P-WELL），一个形成在单元阱上的存储单元阵列（3），并具有存储单元区域（11）和单元阱接触区域（13），第一布线体 BL），以及布置在电池单元接触区域中的第二布线体（CPWELL）。 第二布线体的布局图案与第一布线体的布局图形相同。 电池阱接触区域包括具有与电池阱相同的掺杂剂类型的电池阱触点，并且用作在电池阱接触区域中形成的虚拟晶体管的源极/漏极区域。

公开(公告)号：WO2007079206A3

公开(公告)日：2007-10-04

申请号：PCT/US2006049531

申请日：2006-12-27

Applicant: SANDISK CORP ,  HIGASHITANI MASAAKI ,  PHAM TUAN ,  ICHIGE MASAYUKI ,  HASHIMOTO KOJI ,  TANAKA SATOSHI ,  SUGIMAE KIKUKO

Inventor： HIGASHITANI MASAAKI ,  PHAM TUAN ,  ICHIGE MASAYUKI ,  HASHIMOTO KOJI ,  TANAKA SATOSHI ,  SUGIMAE KIKUKO

IPC: H01L21/8247 ,  G03F7/00 ,  G03F7/20 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/32 ,  H01L27/115

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques, hi one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3F or 5F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F5 and select gates of width 3F spaced apart by 3F or 5F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Abstract translation: 具有例如45-55nm或更小的沟道长度的存储元件的非易失性存储器件利用现有的光刻技术来制造。在一种方法中，第一和第二光掩模的图案被转移到相同的光刻胶层。 例如，第一光掩模可以具有以特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有开口，其尺寸设定为产生期望的选择间栅极间隙，例如3F或5F。 第三光掩模用于在选择栅结构上的第二光刻胶层中提供保护部分。 最终结构具有宽度为F的存储元件，间隔距离为F5，宽度为3F的选择栅极间隔3F或5F。 在另一种方法中，将三个光掩模的图案转移到相应的光致抗蚀剂层以产生类似的最终结构。