公开(公告)号：WO2012129032A1

公开(公告)日：2012-09-27

申请号：PCT/US2012/029133

申请日：2012-03-14

Applicant: SANDISK TECHNOLOGIES, INC. ,  LEE, Sanghyun ,  DUNGA, Mohan ,  HIGASHITANI, Masaaki ,  PHAM, Tuan ,  KREUPL, Franz

Inventor： LEE, Sanghyun ,  DUNGA, Mohan ,  HIGASHITANI, Masaaki ,  PHAM, Tuan ,  KREUPL, Franz

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

Abstract: Non-volatile storage elements having a P-/metal floating gate are disclosed herein. The floating gate may have a P-region near the tunnel oxide, and may have a metal region near the control gate. A P-region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P-region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

Abstract translation: 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮置栅极可以在隧道氧化物附近具有P区，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P区（与强掺杂的p型半导体相反）可以提高相对于P +的擦除效率。

公开(公告)号：WO2008089153A3

公开(公告)日：2008-09-12

申请号：PCT/US2008051017

申请日：2008-01-14

Applicant: SANDISK CORP ,  KAI JAMES ,  METAMIS GEORGE ,  PHAM TUAN DUC ,  HIGASHITANI MASAAKI ,  ORIMOTO TAKASHI

Inventor： KAI JAMES ,  METAMIS GEORGE ,  PHAM TUAN DUC ,  HIGASHITANI MASAAKI ,  ORIMOTO TAKASHI

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/308 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers (620-634) are formed that serve as a mask, for etching one or more layers (604) beneath the spacers. An etch stop pad layer (608) having a material composition substantially similar to the spacer material is provided between a dielectric layer (606) and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract translation: 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成用作掩模的隔板（620-634），用于蚀刻间隔物下面的一个或多个层（604）。 具有与间隔物材料基本相似的材料组成的蚀刻停止衬垫层（608）设置在电介质层（606）和绝缘牺牲层（例如氮化硅）之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：WO2008036484A3

公开(公告)日：2008-08-07

申请号：PCT/US2007076163

申请日：2007-08-17

Applicant: SANDISK CORP ,  CHIEN HENRY ,  MATAMIS GEORGE ,  PHAM TUAN ,  HIGASHITANI MASAAKI ,  HORIUCHI HIDETAKA ,  LUTZE JEFFREY W ,  MOKHLESI NIMA ,  FONG YUPIN KAWING

Inventor： CHIEN HENRY ,  MATAMIS GEORGE ,  PHAM TUAN ,  HIGASHITANI MASAAKI ,  HORIUCHI HIDETAKA ,  LUTZE JEFFREY W ,  MOKHLESI NIMA ,  FONG YUPIN KAWING

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

Abstract translation: 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：WO2007079206A2

公开(公告)日：2007-07-12

申请号：PCT/US2006/049531

申请日：2006-12-27

Applicant: SANDISK CORPORATION ,  HIGASHITANI, Masaaki ,  PHAM, Tuan ,  ICHIGE, Masayuki ,  HASHIMOTO, Koji ,  TANAKA, Satoshi ,  SUGIMAE, Kikuko

Inventor： HIGASHITANI, Masaaki ,  PHAM, Tuan ,  ICHIGE, Masayuki ,  HASHIMOTO, Koji ,  TANAKA, Satoshi ,  SUGIMAE, Kikuko

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques, hi one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3F or 5F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F5 and select gates of width 3F spaced apart by 3F or 5F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Abstract translation: 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择间隙，例如3F或5F。 第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F5的宽度为F的存储元件，并且通过3F或5F隔开的宽度3F的选择栅极。 在另一种方法中，将三个光掩模的图案转移到相应的光刻胶层以产生类似的最终结构。

公开(公告)号：WO2011156695A8

公开(公告)日：2011-12-15

申请号：PCT/US2011/039955

申请日：2011-06-10

Applicant: SANDISK TECHNOLOGIES, INC. ,  HARARI, Eli ,  PHAM, Tuan ,  FONG, Yupin ,  PURAYATH, Vinod, Robert

Inventor： HARARI, Eli ,  PHAM, Tuan ,  FONG, Yupin ,  PURAYATH, Vinod, Robert

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/764

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps (306) may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.

公开(公告)号：WO2008122012A2

公开(公告)日：2008-10-09

申请号：PCT/US2008/059035

申请日：2008-04-01

Applicant: SANDISK CORPORATION ,  KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

Inventor： KAI, James ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  MATAMIS, George ,  ORIMOTO, Takashi

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

Abstract: Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

Abstract translation: 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

公开(公告)号：WO2007075180A1

公开(公告)日：2007-07-05

申请号：PCT/US2006/005629

申请日：2006-02-17

Applicant: SANDISK CORPORATION ,  FANG, Hao ,  PHAM, Tuan ,  HIGASHITANI, Masaaki ,  HEMINK, Gerrit Jan

Inventor： PHAM, Tuan ,  HIGASHITANI, Masaaki ,  HEMINK, Gerrit Jan

IPC: H01L27/115 ,  H01L27/105

CPC classification number: H01L27/11529 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/11526

Abstract: A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

Abstract translation: NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自增强模式进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：WO2007047390A3

公开(公告)日：2007-06-14

申请号：PCT/US2006039931

申请日：2006-10-10

Applicant: SANDISK CORP ,  PHAM TUAN D ,  HIGASHITANI MASAAKI

Inventor： PHAM TUAN D ,  HIGASHITANI MASAAKI

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L21/31111 ,  H01L21/3212 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

Abstract: A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.

Abstract translation: 形成在浮动栅极之间具有浅沟槽隔离结构并且具有在浮动栅极之间延伸的控制栅极的非易失性存储器，其中浅沟槽隔离电介质被蚀刻。 使用离子注入实现蚀刻深度的控制，以与下层电介质相比形成具有高蚀刻速率的电介质层。 在植入期间，导电层覆盖衬底。 存储器阵列中具有小的多晶硅特征的基板和外围区域中的大多晶硅特征使用周边区域中的突起精细地平坦化，并且当突起被去除时停止的软化学机械抛光步骤。

公开(公告)号：WO2005001922A9

公开(公告)日：2007-03-22

申请号：PCT/US2004018545

申请日：2004-06-09

Applicant: SANDISK CORP ,  LUTZE JEFFREY ,  PHAM TUAN ,  CHIEN HENRY ,  MATAMIS GEORGE

Inventor： LUTZE JEFFREY ,  PHAM TUAN ,  CHIEN HENRY ,  MATAMIS GEORGE

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

Abstract: Floating gate structures (230) are disclosed that have a projection that extends away from the surface of a substrate. This projection (232, 234) may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

Abstract translation: 公开了浮动栅极结构（230），其具有远离衬底的表面延伸的突起。 该突起（232,234）可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮动栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。

公开(公告)号：WO2006113036A1

公开(公告)日：2006-10-26

申请号：PCT/US2006/010460

申请日：2006-03-21

Applicant: THE BOEING COMPANY ,  PHAM, Tuan, A.

Inventor： PHAM, Tuan, A.

IPC: H04L29/06

CPC classification number: H04L63/105

Abstract: A method and system for sharing data between networks comprises an interface for receiving data from plural inputs; a policy-based router operationally connected to the interface, the policy-based router assigns security levels to the data based on security characteristics of the inputs and the policy-based router assigns virtual Internet protocol addresses to the data; a memory for retaining the data with the Internet protocol addresses, the memory being operationally connected to the policy-based router; a translator for converting the data into a standard format; and a network stack for transmitting the data to a network. The method includes assigning security levels to the data based on security characteristics of the inputs; assigning virtual Internet protocol addresses to the data; retaining the data with the Internet protocol addresses; converting the data into a standard format; and transmitting the data to a network.

Abstract translation: 用于在网络之间共享数据的方法和系统包括用于从多个输入端接收数据的接口; 基于策略的路由器可操作地连接到接口，基于策略的路由器基于输入的安全特性为数据分配安全级别，并且基于策略的路由器为数据分配虚拟因特网协议地址; 用于使用互联网协议地址保留数据的存储器，所述存储器可操作地连接到基于策略的路由器; 用于将数据转换成标准格式的翻译器; 以及用于将数据发送到网络的网络堆栈。 该方法包括基于输入的安全特性为数据分配安全级别; 为数据分配虚拟互联网协议地址; 使用Internet协议地址保留数据; 将数据转换为标准格式; 并将数据发送到网络。