公开(公告)号：WO2005045892A2

公开(公告)日：2005-05-19

申请号：PCT/US2004035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

Inventor： MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

Abstract translation: 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

公开(公告)号：WO2005045892A3

公开(公告)日：2005-05-19

申请号：PCT/US2004/035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  MATHEW, Leo ,  MORA, Rode, R. ,  NGUYEN, Bich-Yen ,  STEPHENS, Tab, A. ,  VANDOOREN, Anne, M.

Inventor： MATHEW, Leo ,  MORA, Rode, R. ,  NGUYEN, Bich-Yen ,  STEPHENS, Tab, A. ,  VANDOOREN, Anne, M.

IPC: H01L21/00

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer.

公开(公告)号：WO2005045892A9

公开(公告)日：2006-06-22

申请号：PCT/US2004035349

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

Inventor： MATHEW LEO ,  MORA RODE R ,  NGUYEN BICH-YEN ,  STEPHENS TAB A ,  VANDOOREN ANNE M

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer.

Abstract translation: 半导体制造工艺包括形成覆盖衬底的硅片。 形成在鳍片的主面上的栅极电介质。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶并蚀刻通过覆盖层。