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    METHOD OF FABRICATING AIR-GAP SPACER FOR N7/N5 FINFET AND BEYOND
    1.
    发明申请
    METHOD OF FABRICATING AIR-GAP SPACER FOR N7/N5 FINFET AND BEYOND 审中-公开
    制造用于N7 / N5鳍状FETF和更远的空隙间隔物的方法

    公开(公告)号：WO2018080712A1

    公开(公告)日：2018-05-03

    申请号：PCT/US2017/053802

    申请日：2017-09-27

    申请人： APPLIED MATERIALS, INC.

    发明人： CHANG, Chih-Yang ,  HUNG, Raymond Hoiman ,  SATO, Tatsuya E. ,  KIM, Nam Sung ,  SUN, Shiyu ,  WOOD, Bingxi Sun

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49

    CPC分类号： H01L29/7851 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32134 ,  H01L21/32136 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7853

    摘要： Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.

    摘要翻译： 这里公开的实施例涉及具有减小的寄生电容的改进的晶体管。 在一个实施例中，所述晶体管器件包括从衬底的表面突出的三维鳍结构，所述三维鳍结构包括顶表面和两个相对的侧壁，第一绝缘层形成在所述三个 所述牺牲间隔层共形地形成在所述第一绝缘层上，其中所述牺牲间隔层包括氧化铝基材料或氮化钛基材料以及共形地形成在所述牺牲间隔层上的第二绝缘层。 p>

    METHOD OF PATTERNING INTERSECTING STRUCTURES
    3.
    发明申请
    METHOD OF PATTERNING INTERSECTING STRUCTURES 审中-公开
    图案化交互结构的方法

    公开(公告)号：WO2018057493A1

    公开(公告)日：2018-03-29

    申请号：PCT/US2017/052190

    申请日：2017-09-19

    申请人： TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    发明人： VORONIN, Sergey, A. ,  TALONE, Christopher ,  RANJAN, Alok

    IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L29/66

    CPC分类号： H01L21/823431 ,  H01J37/32935 ,  H01J2237/334 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/26 ,  H01L29/66795

    摘要： Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; altematingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.

    摘要翻译： 提供一种在图案化系统中使用集成方案在衬底上图案化结构的方法，所述方法包括：将衬底布置在处理室中，所述衬底具有多个结构和图案， 所述基底包括下层和目标层，至少一个结构与另一个结构相交，每个交点具有交叉角和拐角，所述整合方案在每个交点处需要垂直拐角轮廓; 蚀刻和清洁衬底以将图案转移到目标层上并在每个交叉点处实现目标垂直角轮廓; 在交替和顺序的蚀刻和清洁操作中控制整合方案的选定的两个或更多个操作变量，以实现目标整合目标。

    SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH RELEASED SOURCE AND DRAIN 审中-公开
    具有释放源和漏极的半导体器件

    公开(公告)号：WO2018009162A1

    公开(公告)日：2018-01-11

    申请号：PCT/US2016/040900

    申请日：2016-07-02

    申请人： INTEL CORPORATION

    发明人： RACHMADY, Willy ,  GARDNER, Sanaz K. ,  MOHAPATRA, Chandra S. ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  MA, Sean T. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir

    IPC分类号： H01L29/78 ,  H01L29/423

    CPC分类号： H01L29/785 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775

    摘要： Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

    摘要翻译： 实施例通常针对具有释放源极和漏极的半导体器件。 一种方法的实施例包括：蚀刻半导体器件的缓冲层以在器件的沟道层的栅极沟道部分下方形成栅极沟槽; 用氧化物材料填充栅极沟槽以形成氧化物隔离层; 蚀刻用于所述器件的源极和漏极区域的层间介电（ILD）层中的一个或多个源极/漏极接触沟槽; 刻蚀所述一个或多个源极/漏极接触沟槽内的所述氧化物隔离层以在所述源极和漏极区域中的源极/漏极沟道下方形成一个或多个空腔，其中每个接触沟槽的所述蚀刻将暴露所述源极/ 排水渠道; 以及在一个或多个接触沟槽中沉积接触金属，包括将接触金属沉积在源/漏沟道下方的空腔中。

    NANOWIRE CHANNEL STRUCTURES OF CONTINUOUSLY STACKED NANOWIRES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES
    7.
    发明申请
    NANOWIRE CHANNEL STRUCTURES OF CONTINUOUSLY STACKED NANOWIRES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES 审中-公开
    连续堆叠纳米线用于互补金属氧化物半导体（CMOS）器件的纳米通道结构

    公开(公告)号：WO2017065920A1

    公开(公告)日：2017-04-20

    申请号：PCT/US2016/052039

    申请日：2016-09-16

    申请人： QUALCOMM INCORPORATED

    发明人： XU, Jeffrey, Junhao ,  SONG, Stanley, Seungchul ,  YANG, Da ,  MACHKAOUTSAN, Vladimir ,  BADAROGLU, Mustafa ,  YEAP, Choh, Fei

    IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L21/823821 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/823431 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

    摘要： Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed.In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires.Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire.Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions.A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein.The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint.The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

    摘要翻译： 公开了用于互补金属氧化物半导体（CMOS）器件的连续堆叠纳米线的纳米线沟道结构。在一个方面，示例性CMOS器件包括纳米线沟道结构，纳米线沟道结构包括多个连续堆叠的纳米线。垂直 相邻的纳米线连接在每个纳米线的窄的顶端部分和底端部分。因此，纳米线沟道结构包括比相应的多个中心部分更窄的多个窄部分。环绕纳米线沟道 结构，包括多个窄部分，而不完全缠绕在其中的任何纳米线周围。示例性CMOS器件例如提供比传统鳍式场效应晶体管（FET）（FinFET）更大的有效沟道宽度和更好的栅极控制 示例性的CMOS器件进一步提供了例如比其更短的纳米线沟道结构 一个传统的纳米线FET。

    DEEP EPI ENABLED BY BACKSIDE REVEAL FOR STRESS ENHANCEMENT & CONTACT
    8.
    发明申请
    DEEP EPI ENABLED BY BACKSIDE REVEAL FOR STRESS ENHANCEMENT & CONTACT 审中-公开
    由背压启动的深层EPI应力增强和接触

    公开(公告)号：WO2017052649A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052464

    申请日：2015-09-25

    申请人： INTEL CORPORATION

    发明人： LILAK, Aaron D. ,  CEA, Stephen M. ,  MEHANDRU, Rishabh ,  MORROW, Patrick ,  KEYS, Patrick H.

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

    摘要： Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.

    摘要翻译： 本发明的实施例包括具有应变通道的非平面晶体管和形成这种晶体管的方法。 在一个实施例中，非平面晶体管可以包括半导体衬底。 根据实施例，可以在半导体衬底上形成第一源极/漏极（S / D）区域和第二S / D区域，并且通过沟道区域彼此分离。 可以在通道区域上形成栅极堆叠。 为了增加可能在沟道区域中引起的应变量，实施例可以包括在半导体衬底中形成应变增强开口，从沟道区域下方去除半导体衬底的至少一部分。

    RESISTANCE REDUCTION UNDER TRANSISTOR SPACERS
    9.
    发明申请
    RESISTANCE REDUCTION UNDER TRANSISTOR SPACERS 审中-公开
    电阻间隔下的电阻降低

    公开(公告)号：WO2017052591A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052235

    申请日：2015-09-25

    申请人： INTEL CORPORATION

    发明人： WEBER, Cory E. ,  MORARKA, Saurabh ,  JHAVERI, Ritesh ,  GLASS, Glenn A. ,  LIAO, Szuya S. ,  MURTHY, Anand S.

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.

    摘要翻译： 公开了在晶体管间隔物下进行电阻降低的技术。 在某些情况下，这些技术包括减少源/漏（S / D）掺杂剂暴露于热循环，从而减少S / D掺杂剂对周围材料的扩散和损失。 在一些这样的情况下，这些技术包括延迟掺杂的S / D材料的外延沉积直到晶体管形成工艺流程的结束，从而避免了工艺流程中早期的热循环。 例如，这些技术可以包括用牺牲S / D材料代替S / D区域（例如，用于晶体管S / D的区域中的天然散热材料），然后可以选择性地蚀刻并用高掺杂的外延 S / D材料后期的流程。 在一些情况下，选择性蚀刻可以通过在牺牲S / D上形成在覆盖绝缘体材料上的S / D接触沟槽进行。

    METHOD OF PATTERNING WITHOUT DUMMY GATES
    10.
    发明申请
    METHOD OF PATTERNING WITHOUT DUMMY GATES 审中-公开
    没有DUMMY GATES的方法

    公开(公告)号：WO2017027224A1

    公开(公告)日：2017-02-16

    申请号：PCT/US2016/044474

    申请日：2016-07-28

    申请人： TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    发明人： SMITH, Jeffrey ,  DEVILLIERS, Anton J.

    IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L21/033 ,  H01L21/8234

    CPC分类号： H01L21/0274 ,  H01L21/02603 ,  H01L21/28008 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66795

    摘要： Techniques herein provide precise cuts for fins and nanowires without needing dummy gate pairs to compensate for overlay misalignment. Techniques herein include using an etch mask to remove designated portions of gate structures to define a trench or open space having fin structures, nanowires, etc. The uncovered fin structures are etched away or otherwise removed from the trench segments. The etch mask and material defining the trench provide a combined etch mask for removing uncovered fin portions. Subsequently the trench segments are filled with dielectric material. Without needed dummy gate pairs a given substrate can fit significantly more electrical devices per unit area.

    摘要翻译： 本文的技术提供了用于翅片和纳米线的精确切割，而不需要虚拟门对来补偿重叠的未对准。 本文的技术包括使用蚀刻掩模去除栅极结构的指定部分以限定具有鳍结构，纳米线等的沟槽或开放空间。未覆盖的鳍结构被蚀刻掉或以其它方式从沟槽段移除。 限定沟槽的蚀刻掩模和材料提供用于去除未覆盖的鳍部的组合蚀刻掩模。 随后，沟槽段被电介质材料填充。 没有必要的虚拟门对，给定的基板可以显着增加每单位面积的电气设备。