公开(公告)号：WO2010002515A3

公开(公告)日：2010-07-29

申请号：PCT/US2009044810

申请日：2009-05-21

Applicant: SOITEC SILICON ON INSULATOR ,  MAZURE CARLOS ,  NGUYEN BICH-YEN

Inventor： MAZURE CARLOS ,  NGUYEN BICH-YEN

IPC: H01L21/20

CPC classification number: H01L21/76251

Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

Abstract translation: 在一个实施例中，本发明提供了这样的基板，其被构造成使得在其顶层中制造的器件具有与在标准高电阻率基板中制造的相同器件类似的性质。 本发明的衬底包括具有标准电阻率的支撑体，布置在支撑衬底上的具有高电阻率，优选大于约1000欧姆 - 厘米的半导体层，布置在高电阻率层上的绝缘层，以及顶层 排列在绝缘层上。 本发明还提供了制造这种衬底的方法。

公开(公告)号：WO2010002516A3

公开(公告)日：2010-01-07

申请号：PCT/US2009/044825

申请日：2009-05-21

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  NGUYEN, Bich-yen ,  MAZURE, Carlos

Inventor： NGUYEN, Bich-yen ,  MAZURE, Carlos

IPC: H01L21/20

Abstract: In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

公开(公告)号：WO2007130728A2

公开(公告)日：2007-11-15

申请号：PCT/US2007/062534

申请日：2007-02-22

Applicant: FREESCALE SEMICONDUCTOR INC. ,  SADAKA, Mariam, G. ,  NGUYEN, Bich-yen ,  THEAN, Voon-yew

Inventor： SADAKA, Mariam, G. ,  NGUYEN, Bich-yen ,  THEAN, Voon-yew

IPC: H01L21/31

CPC classification number: H01L21/32 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/84

Abstract: A process of forming an electronic device can include forming a patterned oxidation-resistant layer (124) over a semiconductor layer (106) that overlies a substrate (100), and patterning the semiconductor layer to form a semiconductor island (202, 204, 206, 208). The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material (424) along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.

Abstract translation: 形成电子器件的工艺可以包括在覆盖在衬底（100）上的半导体层（106）上形成图案化的抗氧化层（124），并且图案化半导体层以形成半导体岛（202,204,206 ，208）。 半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。 该方法还可以包括沿着半导体岛的一侧形成抗氧化材料（424）或沿着半导体岛的一侧选择性地沉积半导体材料。 该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛， 并将抗氧化材料转化为含氧环境。

公开(公告)号：WO2006107419A3

公开(公告)日：2006-10-12

申请号：PCT/US2006/005471

申请日：2006-02-16

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  SADAKA, Mariam G. ,  BARR, Alexander L. ,  JOVANOVIC, Dejan ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew ,  THOMAS, Shawn G. ,  WHITE, Ted R.

Inventor： SADAKA, Mariam G. ,  BARR, Alexander L. ,  JOVANOVIC, Dejan ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew ,  THOMAS, Shawn G. ,  WHITE, Ted R.

IPC: H01L21/8238

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

公开(公告)号：WO2006107419A2

公开(公告)日：2006-10-12

申请号：PCT/US2006005471

申请日：2006-02-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  SADAKA MARIAM G ,  BARR ALEXANDER L ,  JOVANOVIC DEJAN ,  NGUYEN BICH-YEN ,  THEAN VOON-YEW ,  THOMAS SHAWN G ,  WHITE TED R

Inventor： SADAKA MARIAM G ,  BARR ALEXANDER L ,  JOVANOVIC DEJAN ,  NGUYEN BICH-YEN ,  THEAN VOON-YEW ,  THOMAS SHAWN G ,  WHITE TED R

IPC: H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract translation: 根据本公开的实施例，制造双应变通道半导体器件（10）的过程包括将应变Si（16）和压缩SiGe（28）与沟槽隔离（24）集成，以实现同时的NMOS和PMOS性能增强 。 如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

公开(公告)号：WO2006039037A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/031000

申请日：2005-08-31

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  THEAN, Voon-Yew ,  SADAKA, Mariam, G. ,  WHITE, Ted, R. ,  BARR, Alexander, L. ,  KOLAGUNTA, Venkat, R. ,  NGUYEN, Bich-Yen ,  VARTANIAN, Victor, H. ,  ZHANG, Da

Inventor： THEAN, Voon-Yew ,  SADAKA, Mariam, G. ,  WHITE, Ted, R. ,  BARR, Alexander, L. ,  KOLAGUNTA, Venkat, R. ,  NGUYEN, Bich-Yen ,  VARTANIAN, Victor, H. ,  ZHANG, Da

IPC: H01L29/94

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Abstract translation: 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：WO2006033746A3

公开(公告)日：2006-03-30

申请号：PCT/US2005/029772

申请日：2005-08-23

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  STEVENS, Tab A. ,  GOOLSBY, Brian J. ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew

Inventor： STEVENS, Tab A. ,  GOOLSBY, Brian J. ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461

Abstract: A metal layer (24) is formed over a metal oxide (14), where the metal oxide is formed over a semiconductor substrate (12). A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings (26) at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer (22) is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.

公开(公告)号：WO2005034230A1

公开(公告)日：2005-04-14

申请号：PCT/US2004/031516

申请日：2004-09-27

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  LIU, Chun-Li ,  BARR, Alexander, L. ,  GRANT, John, M. ,  NGUYEN, Bich-Yen ,  ORLOWSKI, Marius, K. ,  STEPHENS, Tab, A. ,  WHITE, Ted, R. ,  THOMAS, Shawn, G.

Inventor： LIU, Chun-Li ,  BARR, Alexander, L. ,  GRANT, John, M. ,  NGUYEN, Bich-Yen ,  ORLOWSKI, Marius, K. ,  STEPHENS, Tab, A. ,  WHITE, Ted, R. ,  THOMAS, Shawn, G.

IPC: H01L21/335

CPC classification number: H01L29/1054 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/04 ,  H01L29/665 ,  H01L29/7833

Abstract: A semiconductor structure (10) includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer (34) overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material (22) with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also enclosed.

Abstract translation: 半导体结构（10）包括具有第一晶格常数的第一松弛半导体材料的衬底。 半导体器件层（34）覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料（22）。 另外，在基板和半导体器件层之间插入电介质层，其中介电层介于基板和半导体器件层之间，其中介电层包括布置在电介质层内的过渡区，用于在 第一晶格常数和第二晶格常数。 编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度 不超过第二临界厚度。 多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。 也包括制作该方法的方法。

公开(公告)号：WO2013045970A1

公开(公告)日：2013-04-04

申请号：PCT/IB2011/002823

申请日：2011-09-30

Applicant: SOITEC ,  MAZURE, Carlos ,  FERRANT, Richard ,  NGUYEN, Bich-Yen

Inventor： MAZURE, Carlos ,  FERRANT, Richard ,  NGUYEN, Bich-Yen

IPC: G11C8/08 ,  G11C11/408 ,  H03K19/20

CPC classification number: H03K19/20 ,  G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G 1P , G 1N ) and a second (G 2P , G 2N ) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G 2p , G 2N ).

Abstract translation: 本发明涉及一种电路，包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管 第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作 （G2p，G2N）。

公开(公告)号：WO2010002508A1

公开(公告)日：2010-01-07

申请号：PCT/US2009/044365

申请日：2009-05-18

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  NGUYEN, Bich-Yen

Inventor： NGUYEN, Bich-Yen

IPC: H01L27/04

CPC classification number: H01L21/76254 ,  H01L21/76256

Abstract: A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

Abstract translation: 具有较大结晶缺陷密度的支撑体，设置在支撑体正面的第一区域上的绝缘层和设置在绝缘层上的表面层。 可以至少在支撑体的前表面的第二区域上设置附加层，其厚度足以埋设支撑体的结晶缺陷。 衬底还可以包括布置在支撑体的前表面的至少第一区域之间，在支撑体和绝缘层之间的外延层。 此外，通过在表层的第一区域上形成掩模层并除去由掩模层未覆盖的第二区域中的表层和绝缘层来制造衬底的方法。 附加层形成在第二区域中，然后平坦化。