公开(公告)号：WO2007084700A3

公开(公告)日：2007-07-26

申请号：PCT/US2007/001501

申请日：2007-01-19

申请人： UNIVERSITY OF MARYLAND OFFICE OF TECHNOLOGY COMMERCIALIZATION ,  WEN, Xingzhi ,  VISHKIN, Uzi, Yehoshua

发明人： WEN, Xingzhi ,  VISHKIN, Uzi, Yehoshua

IPC分类号： G06F9/48

摘要： An Explicit Multi-Threading (XMT) system and method is provided for processing multiple spawned threads associated with SPAWN-type commands of an XMT program. The method includes executing a plurality of child threads by a plurality of TCUs including a first TCU executing a child thread which is allocated to it; completing execution of the child thread by the first TCU; announcing that the first TCU is available to execute another child thread; executing by a second TCU a parent child thread that includes a nested spawn-type command for spawning additional child threads of the plurality of child threads, wherein the parent child thread is related in a parent-child relationship to the child threads that are spawned in conjunction with the nested spawn-type command; assigning a thread ID (TID) to each child thread, wherein the TID is unique with respect to the other TIDs; and allocating a new child thread to the first TCU.

公开(公告)号：WO2004083904A2

公开(公告)日：2004-09-30

申请号：PCT/US2004/005239

申请日：2004-03-17

申请人： UNIVERSITY OF MARYLAND ,  VISHKIN, Uzi

发明人： VISHKIN, Uzi

IPC分类号： G02B

CPC分类号： G06F13/409 ,  G02B6/43 ,  G06F12/0813 ,  H04B10/801

摘要： A multi-chip processor/memory arrangement replacing a large computer chip, includes a number of modules each including processing elements, registers, and/or memories interconnected by an optical interconnection fabric providing an all-to-all interconnection between the chips, so that the memory cells on each chip represent a portion of shared memory. The optical interconnect fabric is responsible for transporting data between the chips while processing elements on each chip dominate processing. Each chip is manufactured in mass production so that the entire processor/memory arrangement is fabricated in an inexpensive and simplified technology process. The optical communication fabric is based on waveguide technology and includes a number of waveguides, the layout of which follows certain constraints. The waveguides can intersect each other in the single plane, or alternatively, a double layer of waveguide structures and bent over approach may be used. Specific layout patterns of the optical waveguides are presented. The communication of data along the optical communication channels is performed in highly pipelined decentralized routing manner and is envisioned for XMT architecture application.

摘要翻译： 代替大型计算机芯片的多芯片处理器/存储器装置包括多个模块，每个模块包括由提供芯片之间的所有互连的光互连结构互连的处理元件，寄存器和/或存储器，从而 每个芯片上的存储单元表示共享存储器的一部分。 光学互连结构负责在芯片之间传输数据，同时处理每个芯片上的元件主导处理。 每个芯片都是批量生产的，因此整个处理器/存储器装置是以廉价和简化的工艺流程制造的。 光通信结构基于波导技术，并且包括多个波导，其布局遵循某些约束。 波导可以在单个平面中彼此相交，或者可以使用双层波导结构和弯曲方法。 介绍了光波导的具体布局模式。 沿着光通信信道的数据通信以高度流水线分散的路由方式执行，并且被设想用于XMT架构应用。

公开(公告)号：WO2007084700A2

公开(公告)日：2007-07-26

申请号：PCT/US2007001501

申请日：2007-01-19

申请人： UNIV MARYLAND ,  WEN XINGZHI ,  VISHKIN UZI YEHOSHUA

发明人： WEN XINGZHI ,  VISHKIN UZI YEHOSHUA

IPC分类号： G06F9/48

CPC分类号： G06F9/4843

摘要： An Explicit Multi-Threading (XMT) system and method is provided for processing multiple spawned threads associated with SPAWN-type commands of an XMT program. The method includes executing a plurality of child threads by a plurality of TCUs including a first TCU executing a child thread which is allocated to it; completing execution of the child thread by the first TCU; announcing that the first TCU is available to execute another child thread; executing by a second TCU a parent child thread that includes a nested spawn-type command for spawning additional child threads of the plurality of child threads, wherein the parent child thread is related in a parent-child relationship to the child threads that are spawned in conjunction with the nested spawn-type command; assigning a thread ID (TID) to each child thread, wherein the TID is unique with respect to the other TIDs; and allocating a new child thread to the first TCU.

摘要翻译： 提供了一种显式多线程（XMT）系统和方法，用于处理与XMT程序的SPAWN类型命令相关联的多个派生线程。 该方法包括由多个TCU执行多个子线程，所述多个TCU包括执行分配给它的子线程的第一TCU; 由第一TCU完成子线程的执行; 宣布第一个TCU可用于执行另一个子线程; 由第二TCU执行包括用于产生所述多个子线程的附加子线程的嵌套产卵类型命令的父子线程，其中，所述父子线程与子产生父子关系中的子线程相关 与嵌套的spawn-type命令结合使用; 为每个子线程分配线程ID（TID），其中TID相对于其他TID是唯一的; 并为第一个TCU分配一个新的子线程。

公开(公告)号：WO2004083904A3

公开(公告)日：2007-02-01

申请号：PCT/US2004005239

申请日：2004-03-17

申请人： UNIV MARYLAND ,  VISHKIN UZI

发明人： VISHKIN UZI

IPC分类号： H03K19/173 ,  G02B20060101 ,  G06F12/08 ,  G06F13/40 ,  H03K19/00

CPC分类号： G06F13/409 ,  G02B6/43 ,  G06F12/0813 ,  H04B10/801

摘要： A multi-chip processor/memory arrangement (20) is shown which includes a plurality of modules (22), also referred to herein as chips. The modules (22) are interconnected there between by an optical interconnect structure (24) also referred to herein as optical interconnect fabric. The basic concept underlining the structure of the arrangement (20) is to position the processing elements and memory cells on the small chips (22) which are fabricated in mass production based on inexpensive technology, for example, 0.25 micron technology and interconnected with the optical interconnect fabric (24). Packaged with the optical interconnect structure (24), a plurality of inexpensive chips (22) provides sufficient performance but for a small fraction of the cost of the processor/memory argument implemented on a single large computer chips (0.065 micron chip).

摘要翻译： 示出了包括多个模块（22）的多芯片处理器/存储器装置（20），这里也称为芯片。 模块（22）之间通过本文也称为光学互连结构的光学互连结构（24）互连。 布置（20）的结构的基本概念是将处理元件和存储单元定位在基于廉价技术制造的大规模生产的小芯片（22）上，例如0.25微米技术并与光学 互连织物（24）。 利用光学互连结构（24）封装，多个便宜的芯片（22）提供足够的性能，但是在单个大型计算机芯片（0.065微米芯片）上实现的处理器/存储器参数的一小部分成本。

公开(公告)号：WO9843193A3

公开(公告)日：2003-08-07

申请号：PCT/US9805975

申请日：1998-03-20

申请人： UNIV MARYLAND ,  VISHKIN UZI

发明人： VISHKIN UZI

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/45 ,  G06F15/16 ,  G06F15/78 ,  G06F15/80

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (38), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.

摘要翻译： 本发明提出了一种独特的计算范例，其提供了从算法到架构到实现的全谱中利用并行算法中固有的并行性的工具。 本发明提供了一种扩展常规单处理器架构的标准指令集的新的处理架构。 用于实现这种新的计算范例的架构包括线程控制单元（34），产生控制单元（38）和使能指令存储器（50）。 该架构启动多个线程并行执行。 提供线程的控制，使得线程可以被暂停或允许以其自己的速度执行。