公开(公告)号：WO2016045039A1

公开(公告)日：2016-03-31

申请号：PCT/CN2014/087409

申请日：2014-09-25

Applicant: INTEL CORPORATION ,  WANG, Kebing ,  BIAN, Bianny

Inventor： WANG, Kebing ,  BIAN, Bianny

IPC: H04L29/06

CPC classification number: G06F12/0808 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/621

Abstract: A processor includes a first core including a first cache including a cache line, a second core including a second cache, and a cache controller to set a flag stored in a flag section of the cache line of the first cache to one of a processor share (PS) state in response to data stored in the cache line being shared by the second cache, or to a global share (GS) state in response to the data stored in the first cache line being shared by a third cache of a second processor.

Abstract translation: 处理器包括第一核心，其包括包括高速缓存线的第一高速缓存，包括第二高速缓存的第二核心和高速缓存控制器，以将存储在第一高速缓存行的高速缓存行的标志部分中的标志设置为处理器共享之一 响应于存储在由所述第二高速缓存器共享的高速缓存行中的数据或响应于存储在所述第一高速缓存行中的数据被存储在全局共享（GS）状态）的第二高速缓冲存储器 。

公开(公告)号：WO2020061992A1

公开(公告)日：2020-04-02

申请号：PCT/CN2018/108215

申请日：2018-09-28

Applicant: INTEL CORPORATION ,  BIAN, Zhaojuan ,  WANG, Kebing

Inventor： BIAN, Zhaojuan ,  WANG, Kebing

IPC: G06F12/10

Abstract: An apparatus for data processing may be provided, comprising: a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size.

公开(公告)号：WO2015062006A1

公开(公告)日：2015-05-07

申请号：PCT/CN2013/086281

申请日：2013-10-31

Applicant: INTEL CORPORATION ,  WANG, Kebing ,  BIAN, Zhaojuan ,  ZHOU, Wei ,  WANG, Zhihong

Inventor： WANG, Kebing ,  BIAN, Zhaojuan ,  ZHOU, Wei ,  WANG, Zhihong

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，高速缓存存储器的第一部分与第一核心相关联。 该第一高速缓冲存储器部分是分布式高速缓存存储器，并且可以被动态地控制为根据寻址的第一核心的专用高速缓冲存储器和由多个核心（包括第一核心）共享的共享高速缓冲存储器之一 模式，其本身是动态可控的。 描述和要求保护其他实施例。

公开(公告)号：WO2012100373A1

公开(公告)日：2012-08-02

申请号：PCT/CN2011/000135

申请日：2011-01-28

Applicant: INTEL CORPORATION ,  WANG, Kebing ,  YE, Jun ,  HOU, Jinlong

Inventor： WANG, Kebing ,  YE, Jun ,  HOU, Jinlong

IPC: G06T11/40

CPC classification number: G06T1/60 ,  G06T15/04

Abstract: Techniques are described to generate an index for a texture. The index can be used to retrieve a portion of one or more textures from a cache. The index can be adapted based on static texture attributes or direction attributes in order to attempt to achieve texture cache efficiency. Static texture attributes can include, bit are not limited to, 1 - dimensional texture, 2-dimensional texture, 3-dimensional texture, or MIPmaps texture, original memory address. Direction attributes can be, but are not limited to, u-major or v-major directions.

Abstract translation: 描述技术以生成纹理的索引。 索引可用于从缓存中检索一个或多个纹理的一部分。 索引可以基于静态纹理属性或方向属性进行调整，以尝试实现纹理缓存效率。 静态纹理属性可以包括，位不限于1维纹理，2维纹理，3维纹理或MIP贴图纹理，原始存储器地址。 方向属性可以是但不限于u主要或v主要方向。

公开(公告)号：WO2015143658A1

公开(公告)日：2015-10-01

申请号：PCT/CN2014/074167

申请日：2014-03-27

Applicant: INTEL CORPORATION ,  MA, Ling ,  BIAN, Zhaojuan ,  WANG, Zhihong ,  WANG, Kebing

Inventor： MA, Ling ,  BIAN, Zhaojuan ,  WANG, Zhihong ,  WANG, Kebing

IPC: G06F9/38

CPC classification number: G06F9/3808 ,  G06F9/30047 ,  G06F9/3836 ,  G06F12/0875 ,  G06F2212/452

Abstract: A processor includes an execution unit and a filter module. The filter module includes logic to receive an instruction, determine whether the instruction was previously executed to prefetch information from a cache, and discard the instruction based on a determination that the instruction was previously executed to prefetch the information from the cache.

Abstract translation: 处理器包括执行单元和过滤器模块。 滤波器模块包括用于接收指令的逻辑，确定先前是否执行了指令以从高速缓存预取信息，并且基于先前执行指令以从高速缓存预取信息的确定来丢弃该指令。

公开(公告)号：WO2012109770A1

公开(公告)日：2012-08-23

申请号：PCT/CN2011/000254

申请日：2011-02-18

Applicant: INTEL CORPORATION (a corporation of Delaware) ,  WANG, Kebing ,  YE, Jun ,  LI, Jianyu

Inventor： WANG, Kebing ,  YE, Jun ,  LI, Jianyu

IPC: G06F12/00

CPC classification number: G06F12/0875 ,  G06F8/4442 ,  G06F12/0886 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/601 ,  G06T1/60 ,  G06T15/04 ,  G09G5/39

Abstract: Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.

Abstract translation: 描述技术来基于绘制调用的属性和纹理的访问方向来配置高速缓存行结构。 可以考虑绘制调用使用的纹理属性（例如，纹理格式和过滤器类型），采样器和着色器，以确定高速缓存的行大小。 访问方向可以考虑减少用于存储样本请求所需的纹素的行数。