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    NOISE FILTER FOR VIDEO PROCESSING
    3.
    发明申请
    NOISE FILTER FOR VIDEO PROCESSING 审中-公开
    用于视频处理的噪声滤波器

    公开(公告)号：WO2005112434A3

    公开(公告)日：2007-09-27

    申请号：PCT/US2005015402

    申请日：2005-05-03

    Applicant: WIS TECHNOLOGIES INC ,  ZENG WEIMIN ,  SHA LI ,  ZHU PING

    Inventor： ZENG WEIMIN ,  SHA LI ,  ZHU PING

    IPC: G06K9/40 ,  H04N5/21 ,  H04N7/12 ,  H04N7/26 ,  H04N11/02

    CPC classification number: H04N5/21 ,  H04N19/117 ,  H04N19/14

    Abstract: A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.

    Abstract translation: 用于视频处理系统的噪声滤波器包括块选择器，成本计算器，成本表，成本比较器和系数滤波器。 块选择器被耦合以从量化单元接收数据并且选择用于额外滤波的块。 所选择的块被提供给成本计算器使用成本表确定块中的每个系数的成本，并且将成本相加。 成本比较器将总和比较为阈值，并且如果总数大于预设阈值，则使用系数滤波器对系数进行滤波。 然后，VLC单元的噪声滤波器输出滤波器数据。

    SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING
    5.
    发明申请
    SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING 审中-公开
    用于运动矢量预测和残留解码的共享管道结构

    公开(公告)号：WO2006063343A3

    公开(公告)日：2007-05-24

    申请号：PCT/US2005044892

    申请日：2005-12-09

    Applicant: WIS TECHNOLOGIES INC ,  LIN TENG CHIANG ,  ZENG WEIMIN

    Inventor： LIN TENG CHIANG ,  ZENG WEIMIN

    IPC: H04N7/12

    CPC classification number: H04N19/93 ,  H04N19/42 ,  H04N19/52

    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.

    Abstract translation: 提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。 通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。 该架构能够实现更好的性能，并且比传统架构使用更少的内存。 该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

    NOISE FILTER FOR VIDEO PROCESSING
    6.
    发明申请
    NOISE FILTER FOR VIDEO PROCESSING 审中-公开
    用于视频处理的噪声滤波器

    公开(公告)号：WO2005112434A2

    公开(公告)日：2005-11-24

    申请号：PCT/US2005/015402

    申请日：2005-05-03

    Applicant: WIS TECHNOLOGIES, INC. ,  ZENG, Weimin ,  SHA, Li ,  ZHU, Ping

    Inventor： ZENG, Weimin ,  SHA, Li ,  ZHU, Ping

    IPC: H04N5/217

    CPC classification number: H04N5/21 ,  H04N19/117 ,  H04N19/14

    Abstract: A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.

    Abstract translation: 用于视频处理系统的噪声滤波器包括块选择器，成本计算器，成本表，成本比较器和系数滤波器。 块选择器被耦合以从量化单元接收数据并且选择用于额外滤波的块。 所选择的块被提供给成本计算器使用成本表确定块中的每个系数的成本，并且将成本相加。 成本比较器将总和比较为阈值，并且如果总数大于预设阈值，则使用系数滤波器对系数进行滤波。 然后，VLC单元的噪声滤波器输出滤波器数据。

    SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING
    7.
    发明申请
    SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING 审中-公开
    用于运动矢量预测和残留解码的共享管道结构

    公开(公告)号：WO2006063343A2

    公开(公告)日：2006-06-15

    申请号：PCT/US2005/044892

    申请日：2005-12-09

    Applicant: WIS TECHNOLOGIES, INC. ,  LIN, Teng, Chiang ,  ZENG, Weimin

    Inventor： LIN, Teng, Chiang ,  ZENG, Weimin

    IPC: H04N11/02 ,  H04N11/04 ,  H04B1/66 ,  H04N7/12

    CPC classification number: H04N19/93 ,  H04N19/42 ,  H04N19/52

    Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.

    Abstract translation: 提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。 通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。 该架构能够实现更好的性能，并且比传统架构使用更少的内存。 该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

    DIGITAL SIGNAL PROCESSING STRUCTURE FOR DECODING MULTIPLE VIDEO STANDARDS
    8.
    发明申请
    DIGITAL SIGNAL PROCESSING STRUCTURE FOR DECODING MULTIPLE VIDEO STANDARDS 审中-公开
    用于解码多个视频标准的数字信号处理结构

    公开(公告)号：WO2006063260A2

    公开(公告)日：2006-06-15

    申请号：PCT/US2005/044683

    申请日：2005-12-09

    Applicant: WIS TECHNOLOGIES, INC. ,  LIN, Teng, Chiang ,  YUAN, Hongjun ,  ZENG, Weimin ,  PENG, Liang

    Inventor： LIN, Teng, Chiang ,  YUAN, Hongjun ,  ZENG, Weimin ,  PENG, Liang

    IPC: H04N11/04 ,  H04N7/12 ,  H04N11/02 ,  H04B1/66

    CPC classification number: H04N19/436 ,  H04N19/12 ,  H04N19/136 ,  H04N19/172 ,  H04N19/423 ,  H04N19/44 ,  H04N19/61

    Abstract: In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.

    Abstract translation: 在一个实施例中，DSP结构包括四个主要部分：DEQ，行的IDCT，列的IDCT和运动补偿。 数据输入序列以便于将数据加载到行IDCT和列IDCT的硬件结构中的方式组织。 通过DSP结构启用两种类型的解码流程：H.264解码流（例如，逆量化，逆离散Hadamard变换，帧内预测和运动失真），以及非H.264解码流（例如，逆量化，行反向 离散余弦变换，列逆离散余弦变换和运动失真）。 非H.264解码流可用于MPEG1 / 2/4，H.263，Microsoft WMV9和Sony Digital Video等标准。

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