公开(公告)号：WO2014043137A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/059083

申请日：2013-09-10

Applicant: ADESTO TECHNOLOGIES CORPORATION

Inventor： KOUSHAN, Foroozan Sarah ,  VAN BUSKIRK, Michael A.

IPC: G11C11/24

CPC classification number: G11C13/0011 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/74 ,  G11C2213/79

Abstract: A method of operating a memory cell can include applying a select pulse at a gate of a select transistor having a first node and a second node, the first node coupled to the first access terminal of the access device, wherein the second node is coupled to a bit line potential node; charging a capacitor having a first plate and a second plate, the first plate coupled to the first node of the select transistor and to the first access terminal of the access device during the select pulse; activating the access device after charging the capacitor; deactivating the select transistor after activating the access device; and discharging the charged capacitor through the resistive switching device.

Abstract translation: 操作存储器单元的方法可以包括在具有第一节点和第二节点的选择晶体管的栅极处施加选择脉冲，第一节点耦合到接入设备的第一接入终端，其中第二节点耦合到 位线势点; 对具有第一板和第二板的电容器充电，所述第一板耦合到选择晶体管的第一节点并且在选择脉冲期间耦合到接入装置的第一接入终端; 在对电容器充电后激活接入设备; 激活接入设备后去激活选择晶体管; 并通过电阻式开关装置对充电的电容器进行放电。

公开(公告)号：WO2014137943A2

公开(公告)日：2014-09-12

申请号：PCT/US2014/020034

申请日：2014-03-03

Applicant: ADESTO TECHNOLOGIES CORPORATION

Inventor： LEE, Wei Ti ,  WANG, Janet ,  GOPALAN, Chakravarthy ,  SHIELDS, Jeffrey Allan ,  MA, Yi ,  TSAI, Kuei Chang ,  SANCHEZ, John ,  JAMESON, John Ross ,  VAN BUSKIRK, Michael A. ,  GOPINATH, Venkatesh P.

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

Abstract: A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.

Abstract translation: 可编程在不同阻抗状态之间的存储元件可包括第一电极; 开关层，与所述第一电极接触并且包括至少一种金属氧化物; 以及与开关层接触的缓冲层。 缓冲层可以包括分布在缓冲层内的第一金属，碲，第三元素和第二金属。 第二电极可以与缓冲层接触。

公开(公告)号：WO2017015333A1

公开(公告)日：2017-01-26

申请号：PCT/US2016/043080

申请日：2016-07-20

Applicant: ADESTO TECHNOLOGIES CORPORATION

Inventor： RAMSBEY, Mark T. ,  GOPINATH, Venkatesh P. ,  SHIELDS, Jeffrey Allan ,  TSAI, Kuei Chang ,  GOPALAN, Chakravarthy ,  VAN BUSKIRK, Michael A.

IPC: G11C13/00

CPC classification number: H01L45/085 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/79 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253

Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Abstract translation: 集成电路装置可以包括形成在具有连接到在第一方向上延伸的字线的控制端子的基板中的多个存取晶体管; 形成在所述基板上的多个两端可编程阻抗元件; 至少一个导电板结构形成在可编程阻抗元件上并具有至少第一方向的共同导电连接; 多个存储触点，其从每个存取晶体管的第一电流端子延伸到可编程阻抗元件之一; 形成在所述至少一个导电板结构上的多个位线，所述位线沿与第一方向不同的第二方向延伸; 以及从每个存取晶体管的第二电流端通过至少一个板结构中的开口延伸到位线之一的多个位线触点。