公开(公告)号：WO2019125587A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/055516

申请日：2018-10-11

申请人： HRL LABORATORIES, LLC

发明人： HERRAULT, Florian G. ,  BROWN, David ,  SHARIFI, Hasan ,  WONG, Joel C. ,  REGAN, Dean C. ,  TANG, Yan ,  FUNG, Helen

IPC分类号： H01L25/065 ,  H01L23/482 ,  H01L23/13 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/4827 ,  H01L24/27 ,  H01L25/50 ,  H01L2221/68354

摘要： An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by an attachment material attaching at least one wall of the through-wafer cavity to at least one of the component chip bottom surface and a component chip side surface; said component chip comprising at least one component contact pad on said component chip top substrate; a first conductor connecting said wafer contact pad and said component contact pad.

公开(公告)号：WO2019123152A1

公开(公告)日：2019-06-27

申请号：PCT/IB2018/060058

申请日：2018-12-13

申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

发明人： HUSSAIN, Muhammad Mustafa

IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L21/02 ,  H01L27/06 ,  H01L21/822 ,  G01P15/18

CPC分类号： H01L25/065 ,  G01P15/18 ,  H01L21/8221 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06555 ,  H01L2225/06579

摘要： A monolithic electronic device includes a plurality of rigid portions arranged in a polyhedron shape and a plurality of in-plane and out-of-plane deformable portions connecting the plurality of rigid portions to each other. Each of the plurality of rigid portions has an outer side and an opposing inner side. The inner of each of the plurality of rigid portions face an inside of the polyhedron shape. At least some of the plurality of rigid portions include semiconductor devices on both the outer and inner sides. The plurality of rigid portions and the plurality of in-plane and out-of-plane deformable portions are monolithic.

公开(公告)号：WO2018182847A1

公开(公告)日：2018-10-04

申请号：PCT/US2018/016434

申请日：2018-02-01

申请人： QUALCOMM INCORPORATED

发明人： KAMAL, Pratyush ,  SAMADI, Kambiz ,  XIE, Jing ,  DU, Yang

IPC分类号： H01L23/528 ,  H01L25/065 ,  H01L21/98 ,  H01L27/06

CPC分类号： H01L25/0657 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/014 ,  H01L2924/00014

摘要： Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：WO2018063641A2

公开(公告)日：2018-04-05

申请号：PCT/US2017/048921

申请日：2017-08-28

申请人： INTEL CORPORATION

发明人： CHIU, Chia-Pin ,  TOMITA, Yoshihiro ,  SEKIHARA, Yoko ,  SANKMAN, Robert L.

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052

摘要： An apparatus is described that includes a package on package structure. The package on package structure includes an interposer to implement electrical interconnections between an upper package of the package on package structure and a lower package of the package on package structure. The interposer has packed wires, the packed wires have respective polygonal cross sections.

摘要翻译： 描述了包括封装件封装结构的装置。 封装上封装结构包括内插器以实现封装上封装结构的上封装和封装上封装结构的下封装之间的电互连。 插入器具有包装线，包装线具有各自的多边形横截面。

公开(公告)号：WO2017123284A1

公开(公告)日：2017-07-20

申请号：PCT/US2016/052769

申请日：2016-09-21

申请人： ADVANCED MICRO DEVICES, INC.

发明人： JAYASENA, Nuwan S. ,  ROBERTS, David A.

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/12

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105

摘要： The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.

摘要翻译： 所描述的实施例包括具有位于其中的信号路由的中介层。 插入器包括按照图案排列的一组站点，每个站点包括一组连接点。 每个站点中的每个连接点都耦合到相应的一个信号路由。 集成电路小芯片可以安装在位置上，并且用于安装的集成电路小芯片的信号连接器可以耦合到对应位置的一些或全部连接点，从而将小芯片耦合到对应的信号路由。 小芯片然后可以经由连接点和信号路线发送和接收信号。 在一些实施例中，每个站点中的一组连接点是相同的，即具有相同的物理布局。 在其他实施例中，每个站点的连接点集合被布置在两个或更多个物理布局中的一个中。

公开(公告)号：WO2017108121A1

公开(公告)日：2017-06-29

申请号：PCT/EP2015/081130

申请日：2015-12-23

申请人： INTEL IP CORPORATION ,  ALBERS, Sven ,  REINGRUBER, Klaus ,  PATTEN, Richard ,  SEIDEMANN, Georg ,  GEISSLER, Christian

发明人： ALBERS, Sven ,  REINGRUBER, Klaus ,  PATTEN, Richard ,  SEIDEMANN, Georg ,  GEISSLER, Christian

IPC分类号： H01L23/498 ,  H01L25/065

CPC分类号： H01L24/92 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08237 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2401 ,  H01L2224/24145 ,  H01L2224/245 ,  H01L2224/73259 ,  H01L2224/80815 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9222 ,  H01L2224/92224 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/014 ,  H01L2224/80001 ,  H01L2224/19 ,  H01L2924/00012

摘要： An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

摘要翻译： 描述了包括半导体管芯封装的设备。 半导体管芯封装包括具有顶侧和底侧的半导体管芯封装衬底。 半导体管芯封装包括在半导体管芯封装衬底的底侧上的I / O球。 I / O球将安装到平面板上。 半导体管芯封装包括安装在半导体管芯封装衬底的底侧上的第一半导体管芯。 第一半导体管芯垂直地位于半导体管芯封装衬底的底侧和作为半导体管芯封装的一部分的第二半导体管芯之间。

公开(公告)号：WO2017107176A1

公开(公告)日：2017-06-29

申请号：PCT/CN2015/098870

申请日：2015-12-25

申请人： INTEL CORPORATION ,  GUO, Mao

发明人： GUO, Mao

IPC分类号： H01L23/48

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire(50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

摘要翻译： 描述微电子结构（200）和微电子制造方法。 第一封装（10）具有形成在第一基础层（12）上的第一导电焊盘（40,41,47,48）。 导线（50-53）与第一基底层（12）的第一导电垫（（40,41,47,48））引线键合，在第一基底层（12）上形成模盖（70） 在模帽（70）中形成通孔（90-93）以到达导线（50-53）。焊接结构（80-83）耦合到导线（50-53）。 通过将第二封装（100）的第二焊料结构（110-113）附着到第一封装（10）的第一焊料结构（80-83），第二封装（100）连接到第一封装（10）

公开(公告)号：WO2017107174A1

公开(公告)日：2017-06-29

申请号：PCT/CN2015/098867

申请日：2015-12-25

申请人： INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin

发明人： DING, Zhicheng ,  LIU, Bin

IPC分类号： H01L25/16

CPC分类号： H01L25/16 ,  H01L22/14 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

摘要： A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

摘要翻译：

封装中的系统和封装中的系统。 多个无源器件耦合到插入器。 模制化合物包封多个无源器件并限定具有基本上平坦的表面的平台。 内插器耦合到衬底。 多个集成电路管芯以堆叠方式耦合到平面表面。

公开(公告)号：WO2017091696A1

公开(公告)日：2017-06-01

申请号：PCT/US2016/063533

申请日：2016-11-23

申请人： ARCTIC SAND TECHNOLOGIES, INC.

发明人： GIULIANO, David

IPC分类号： H02M3/07

CPC分类号： H02M3/07 ,  H01L23/64 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1035 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H02M3/155 ,  H02M3/335 ,  H02M2001/007 ,  H01L2924/014 ,  H01L2924/00014

摘要： An apparatus comprises a charge pump packaged with a load that receives charge provided by the charge pump, the charge pump comprising a plurality of switches that, when connected to a plurality of capacitors, cause the plurality of capacitors to assume a selected configuration, wherein the switches are configured to cause transitions between configurations of the capacitors.

摘要翻译： 一种装置包括与负载接收的电荷泵，所述负载接收由所述电荷泵提供的电荷，所述电荷泵包括多个开关，所述开关在连接到多个电容器时使所述多个电容器 以采取选定的配置，其中开关被配置为引起电容器配置之间的转换。

公开(公告)号：WO2017083015A1

公开(公告)日：2017-05-18

申请号：PCT/US2016/053083

申请日：2016-09-22

申请人： INTEL CORPORATION

发明人： SAHASRABUDHE, Shubhada H. ,  SANE, Sandeep B. ,  KUMAR, Siddarth ,  TANDON, Shalabh

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/488

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

摘要： Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

摘要翻译： 这里通常讨论的是用于通过模具互连（TMI）更可靠地封装（PoP）封装的方法和设备。 器件可以包括第一管芯封装和第二管芯封装，第一管芯封装包括在第一管芯封装上或者至少部分地在第一管芯封装中的第一导电焊盘，在第一管芯封装上的电介质模制材料，模制材料包括穿过其中的至少部分地暴露焊盘的孔， 包括在第二管芯上或至少部分地在第二管芯中的第二导电焊盘的管芯封装将第二管芯封装封装在模具材料上，使得第二导电焊盘通过孔面对第一导电焊盘，并且在孔中形成形状记忆结构， 第一管芯封装和第二管芯封装之间的焊料柱电连接的一部分。