公开(公告)号：WO2022187239A1

公开(公告)日：2022-09-09

申请号：PCT/US2022/018331

申请日：2022-03-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： NG, Philip ,  RAVAL, Nippon ,  XU, Buheng ,  DOBRIN, Rostislav S. ,  HAN, Shawn

IPC: G06F9/455 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/14 ,  G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a plurality of input/output memory manage units (IOMMUs), each of the plurality of IOMMUs coupled to the data fabric; a plurality of root ports, each of the root ports coupled to a corresponding IOMMU of the plurality of IOMMUs; and a plurality of peripheral component endpoints, each of the plurality of peripheral component endpoints coupled to a corresponding root port of the plurality of root ports, wherein each of the root ports comprises hardware control logic operative to: synchronize the plurality of root ports; receive, from the corresponding peripheral component endpoint, a direct memory access (DMA) request; and provide the DMA request to the corresponding IOMMU of the plurality of IOMMUs.

公开(公告)号：WO2022144646A1

公开(公告)日：2022-07-07

申请号：PCT/IB2021/061534

申请日：2021-12-09

Applicant: ATI TECHNOLOGIES ULC

Inventor： NG, Philip ,  RAVAL, Nippon

IPC: G06F12/02

Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.

公开(公告)号：WO2022200962A1

公开(公告)日：2022-09-29

申请号：PCT/IB2022/052503

申请日：2022-03-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： NG, Philip ,  RAVAL, Nippon

IPC: G06F12/08 ,  G06F12/1009

Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory accessible by at least one IO device in the memory, the software entity and the PME setting migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. The PME migrates the page of memory upon completing the operations for preparing to migrate the page of memory.