公开(公告)号：WO2022187239A1

公开(公告)日：2022-09-09

申请号：PCT/US2022/018331

申请日：2022-03-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： NG, Philip ,  RAVAL, Nippon ,  XU, Buheng ,  DOBRIN, Rostislav S. ,  HAN, Shawn

IPC: G06F9/455 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/14 ,  G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a plurality of input/output memory manage units (IOMMUs), each of the plurality of IOMMUs coupled to the data fabric; a plurality of root ports, each of the root ports coupled to a corresponding IOMMU of the plurality of IOMMUs; and a plurality of peripheral component endpoints, each of the plurality of peripheral component endpoints coupled to a corresponding root port of the plurality of root ports, wherein each of the root ports comprises hardware control logic operative to: synchronize the plurality of root ports; receive, from the corresponding peripheral component endpoint, a direct memory access (DMA) request; and provide the DMA request to the corresponding IOMMU of the plurality of IOMMUs.