公开(公告)号：WO2019108284A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/048187

申请日：2018-08-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： MORTON, Eric Christopher ,  COOPER, Elizabeth ,  WALKER, William L. ,  HUNT, Douglas Benson ,  BORN, Richard Martin ,  LEE, Richard H. ,  MIRANDA, Paul C. ,  NG, Philip

IPC: G06F12/0815 ,  G06F12/0862

Abstract: A method for steering data for an I/O write operation (144) includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric (102), a cache (122, 123, 124, 126) as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration (156) implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data via a fetch operation (152) while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

公开(公告)号：WO2022187239A1

公开(公告)日：2022-09-09

申请号：PCT/US2022/018331

申请日：2022-03-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： NG, Philip ,  RAVAL, Nippon ,  XU, Buheng ,  DOBRIN, Rostislav S. ,  HAN, Shawn

IPC: G06F9/455 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/14 ,  G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a plurality of input/output memory manage units (IOMMUs), each of the plurality of IOMMUs coupled to the data fabric; a plurality of root ports, each of the root ports coupled to a corresponding IOMMU of the plurality of IOMMUs; and a plurality of peripheral component endpoints, each of the plurality of peripheral component endpoints coupled to a corresponding root port of the plurality of root ports, wherein each of the root ports comprises hardware control logic operative to: synchronize the plurality of root ports; receive, from the corresponding peripheral component endpoint, a direct memory access (DMA) request; and provide the DMA request to the corresponding IOMMU of the plurality of IOMMUs.

公开(公告)号：WO2013081942A1

公开(公告)日：2013-06-06

申请号：PCT/US2012/066360

申请日：2012-11-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： KEGEL, Andrew ,  HUMMEL, Mark ,  ASARO, Anthony ,  NG, Philip

IPC: G06F13/28 ,  G06F12/00

CPC classification number: G06F13/28 ,  G06F12/0223 ,  G06F12/1081 ,  G06F2213/0058

Abstract: The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non- system memory for use by the I/O device to perform the DMA.

Abstract translation: 本系统使得输入/输出（I / O）设备能够请求存储器来执行系统存储器的直接存储器访问（DMA）。 此外，系统使用输入/输出存储器管理单元（IOMMU）来确定系统存储器是否可用。 如果系统内存不可用，IOMMU将通知与系统内存相关联的操作系统，以便操作系统分配非系统内存供I / O设备使用以执行DMA。

公开(公告)号：WO2022212182A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/021818

申请日：2022-03-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： WHITE, Sean T. ,  NG, Philip

IPC: G06F12/121 ,  G06F13/28 ,  G06F12/063 ,  G06F12/0811 ,  G06F12/0882 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F9/45545 ,  G06F9/45558

Abstract: Methods and apparatus for providing page migration of pages among tiered memories identify frequently accessed memory pages in each memory tier and generate page hotness ranking information indicating how frequently memory pages are being accessed. Methods and apparatus provide the page hotness ranking information to an operating system or hypervisor depending on which is used in the system, the operating system or hypervisor issues a page move command to a hardware data mover, based on the page hotness ranking information and the hardware data mover moves a memory page to a different memory tier in response to the page move command from the operating system.

公开(公告)号：WO2021035134A1

公开(公告)日：2021-02-25

申请号：PCT/US2020/047376

申请日：2020-08-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： ARORA, Sonu ,  BLINZER, Paul ,  NG, Philip ,  RAVAL, Nippon Harshadk

IPC: G06F12/109 ,  G06F12/1027 ,  G06F12/1009 ,  G06T1/60

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：WO2020122988A1

公开(公告)日：2020-06-18

申请号：PCT/US2019/039433

申请日：2019-06-27

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： NG, Philip ,  KALYANASUNDHARAM, Vydhyanathan

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0831 ,  G06F12/0842

Abstract: Bus protocol features are provided for chaining memory access requests on a high speed interconnect bus, allowing for reduced signaling overhead. Multiple memory request messages are received over a bus. A first message has a source identifier, a target identifier, a first address, and first payload data. The first payload data is stored in a memory at locations indicated by the first address. Within a selected second one of the request messages, a chaining indicator is received associated with the first request message and second payload data. The second request message does not include an address. Based on the chaining indicator, a second address for which memory access is requested is calculated based on the first address. The second payload data is stored in the memory at locations indicated by the second address.

公开(公告)号：WO2012082864A1

公开(公告)日：2012-06-21

申请号：PCT/US2011/064854

申请日：2011-12-14

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC ,  KEGEL, Andy ,  HUMMEL, Mark ,  GLASER, Steve ,  ASARO, Anthony ,  NG, Philip ,  CHENG, Jeffrey

Inventor： KEGEL, Andy ,  HUMMEL, Mark ,  GLASER, Steve ,  ASARO, Anthony ,  NG, Philip ,  CHENG, Jeffrey

IPC: G06F12/10

CPC classification number: G06F12/109 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/151

Abstract: Embodiments of the present invention provide methods, systems, and computer readable media for input output memory management unit (IOMMU) two-layer addressing in the context of memory address translations for I/O devices. According to an embodiment, a method includes translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a guest address translation table according to a process address space identifier associated with an address translation transaction associated with an I/O device, and translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

Abstract translation: 本发明的实施例提供了用于I / O设备的存储器地址转换的上下文中的输入输出存储器管理单元（IOMMU）双层寻址的方法，系统和计算机可读介质。 根据实施例，一种方法包括根据与与I / O相关联的地址转换事务相关联的进程地址空间标识符，使用访客地址转换表将访客虚拟地址（GVA）翻译成相应的客体物理地址（GPA） 设备，并且根据与地址转换事务相关联的设备标识符，使用系统地址转换表将GPA转换为相应的系统物理地址（SPA）。

公开(公告)号：WO2018075535A1

公开(公告)日：2018-04-26

申请号：PCT/US2017/057005

申请日：2017-10-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： KAPLAN, David ,  CHAN, Maggie ,  NG, Philip

IPC: G06F21/62 ,  G06F21/60 ,  G06F9/455

Abstract: A processor [102] employs a hardware encryption module [120] in the memory access path between an input/out device [106] and memory [104] to cryptographically isolate secure information. In some embodiments, the encryption module is located at a memory controller [116] of the processor, and each memory access request provided to the memory controller includes VM tag value identifying the source of the memory access request. The VM tag is determined based on a requestor id identifying the source of the memory access request. The encryption module performs encryption (for write accesses) or decryption (for read accesses) of the data associated with the memory access based on an encryption key associated with the VM tag.

Abstract translation: 处理器[102]在输入/输出设备[106]和存储器[104]之间的存储器访问路径中采用硬件加密模块[120]来加密隔离安全信息。 在一些实施例中，加密模块位于处理器的存储器控​​制器[116]处，并且提供给存储器控制器的每个存储器访问请求包括标识存储器访问请求的源的VM标签值。 VM标签基于标识存储器访问请求的来源的请求者ID来确定。 加密模块基于与VM标签相关联的加密密钥执行与存储器访问相关联的数据的加密（用于写入访问）或解密（用于读取访问）。

公开(公告)号：WO2015061731A1

公开(公告)日：2015-04-30

申请号：PCT/US2014/062249

申请日：2014-10-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  NG, Philip ,  CHAN, Maggie ,  CUEVA, Vincent ,  CHEN, Liang ,  ASARO, Anthony ,  MIRZA, Jimshed ,  DONLEY, Greggory Douglas ,  BROUSSARD, Bryan ,  TSIEN, Benjamin ,  ADIRI, Yaniv

IPC: G06F12/02 ,  G06F12/06 ,  G11C7/10

CPC classification number: G06F12/1009 ,  G06F12/1045 ,  G06F12/12 ,  G06F2212/684

Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/ probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

Abstract translation: 本发明通过新的原子测试[0]和OR和Mask来提供在硬件中的页表访问和脏位管理。 本发明还提供了一种使ACE能够进行CCI翻译的垫圈。 该垫片进一步提供了ACE和CCI之间的请求转换，针对受害者和探针冲突的死锁避免，ARM屏障处理和电源管理交互。 本发明还提供了一种用于ARM受害者/探测器碰撞处理的解决方案，其使统一的北桥陷入僵局。 这些解决方案包括一个专用的回写虚拟通道，使用4跳协议的IO请求的探测器和MCT中的WrBack重新排序能力，其中受害者通过数据通过请求时更新旧的请求。

公开(公告)号：WO2013081884A1

公开(公告)日：2013-06-06

申请号：PCT/US2012/065860

申请日：2012-11-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI Technologies ULC

Inventor： KEGEL, Andrew ,  HUMMEL, Mark ,  ASARO, Anthony ,  NG, Philip

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies.

Abstract translation: 本系统使得能够通过输入/输出存储器管理单元（IOMMU）将与访问存储器中的数据相关联的指针传递到输入/输出（I / O）设备。 I / O设备通过IOMMU访问存储器中的数据，而不将数据复制到本地I / O设备存储器中。 I / O设备可以基于指针对存储器中的数据执行操作，使得I / O设备访问存储器而不需要昂贵的副本。