公开(公告)号：WO1998012624A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002257

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/30

CPC classification number: G06F7/57 ,  G06F7/49921 ,  G06F7/49994 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/3877

Abstract: A data processing system is provided including an arithmetic logic unit (20, 22, 24) receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N = 3,8

Abstract translation: 提供了一种数据处理系统，包括从M×位寄存器接收输入操作数的算术逻辑单元（20,22,24），以产生存储在N个Y位寄存器内的输出数据字，其中M / N = = YX

公开(公告)号：WO1998012628A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002261

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/302

CPC classification number: G06F9/30112 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30127 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/30185 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A data processing system having a plurality of registers (10) and an arithmetic logic unit (20, 22, 24) is responsive to program instruction words. At least one program instruction word includes a destination register bit field specifying a destination register of a result data word and a destination register write disable flag for disabling writing of that result data word to the destination register.

Abstract translation: 具有多个寄存器（10）和算术逻辑单元（20,22,24）的数据处理系统响应于程序指令字。 至少一个程序指令字包括指定结果数据字的目的地寄存器的目标寄存器位字段和用于禁止将该结果数据字写入到目标寄存器的目的寄存器写禁止标志。

公开(公告)号：WO1998012627A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002260

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/302

CPC classification number: G06F9/30014 ,  G06F7/48 ,  G06F9/30025 ,  G06F9/30036

Abstract: A data processing system having a plurality of registers (10) and an arithmetic logic unit (20, 22, 24) includes program instruction words having a source register bit field Sn specifying one of the registers storing an input operand data word together with an input operand size flag indicating whether the input operand has a N-bit size or (N/2)-bit size together with a high/low location flag indicating which of the high order bit positions or low order bit positions stores the input operand if it is of the smaller size. It is preferred that the arithmetic logic unit is also able to perform parallel operation program instruction words operating independently upon (N/2)-bit input operand data words stored in respective halves of a register.

Abstract translation: 具有多个寄存器（10）和算术逻辑单元（20,22,24）的数据处理系统包括具有源寄存器位字段Sn的程序指令字，其指定存储输入操作数数据字的寄存器之一以及输入 指示输入操作数是否具有N位大小或（N / 2）位大小以及指示高位位置或低位位置存储输入操作数的高/低位置标志，如果它 尺寸较小。 优选地，算术逻辑单元还能够执行独立于存储在寄存器的相应两半中的（N / 2）位输入操作数数据字独立运行的并行操作程序指令字。

公开(公告)号：WO1998012629A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002259

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/38

CPC classification number: G06F9/3877 ,  G06F17/10

Abstract: A digital signal processing system is described in which a microprocessor unit (2) operating under control of microprocessor program instruction words controls data transfer to and from a data storage device (8) and the supply and fetching of data to and from a digital signal processing unit (4).

Abstract translation: 描述了一种数字信号处理系统，其中在微处理器程序指令字的控制下操作的微处理器单元（2）控制数据传输到数据存储设备（8）和从数据存储设备（8）传送数据，并向数据信号处理和从数据信号处理提供和取出数据 单位（4）。

公开(公告)号：WO1998012626A1

公开(公告)日：1998-03-26

申请号：PCT/GB1997002256

申请日：1997-08-22

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian ,  GLASS, Simon, James

IPC: G06F09/302

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3842 ,  G06F9/3893

Abstract: A data processing system incorporating an arithmetic logic unit (20, 22, 24) having an N-bit data pathway and supporting parallel operation program instruction words in which to independent arithmetic operations are carried out in parallel by the arithmetic logic unit upon (N/2)-bit input operand words. Two sets of condition code flags N, Z, C V, SN, SZ, SC, SV responsive to the separate arithmetic logic operations are provided.

Abstract translation: 一种包含具有N位数据通路的算术逻辑单元（20,22,24）和支持并行操作程序指令字的数据处理系统，其中独立算术运算由算术逻辑单元并行地执行（N / 2）位输入操作数字。 提供响应于分离的算术逻辑运算的两组条件码标志N，Z，C V，SN，SZ，SC，SV。

公开(公告)号：WO1995030188A1

公开(公告)日：1995-11-09

申请号：PCT/GB1995000315

申请日：1995-02-15

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian

IPC: G06F09/318

CPC classification number: G06F9/3822 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

Abstract: A data processing system is described utilising two instruction sets. Both instruction sets control processing using full N-bit data pathways within a processor core (2). One instruction set is a 32-bit instruction set and the other is a 16-bit instruction set. Both instruction sets are permanently installed and have associated instruction decoding hardware (30, 36, 38).

Abstract translation: 利用两个指令集来描述数据处理系统。 两个指令集都使用处理器核心（2）内的全N位数据通路进行控制处理。 一个指令集是32位指令集，另一个是16位指令集。 两个指令集都是永久安装的，并具有相关的指令解码硬件（30,36,38）。

公开(公告)号：WO1995030187A1

公开(公告)日：1995-11-09

申请号：PCT/GB1995000314

申请日：1995-02-15

Applicant: ADVANCED RISC MACHINES LIMITED

Inventor： ADVANCED RISC MACHINES LIMITED ,  JAGGAR, David, Vivian

IPC: G06F09/318

CPC classification number: G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

Abstract: A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core (2) via an instruction pipeline (6). As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.

Abstract translation: 利用多个指令集描述数据处理系统。 程序指令字通过指令流水线（6）提供给处理器核心（2）。 当第二指令集的程序指令字沿着指令流水线传递时，它们被映射到第一指令集的程序指令字。 第二指令集具有比第一指令集小的位大小的程序指令字，并且是第一指令集的子集。 较小的位大小提高了代码密度，而作为第一指令集的子集的第二指令集的性质使得能够有效地执行一对一映射，因此避免了对于第二指令集的专用指令解码器的需要 。