公开(公告)号：WO1997048262A1

公开(公告)日：1997-12-18

申请号：PCT/JP1997001665

申请日：1997-05-19

Applicant: ADVANTEST CORPORATION ,  KOBAYASHI, Satoshi

Inventor： ADVANTEST CORPORATION

IPC: H05K09/00

CPC classification number: H05K9/0018 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49169

Abstract: A method of reducing electromagnetic waves radiated from a cable receiving opening of an electronic device, that easily improves the electromagnetic wave shielding effect, regardless of the number of cables, and facilitates cable connection/disconnection. A soft electromagnetic shielding conductive cloth (15) is provided to cover completely the opening (12). The opening (12) is formed in the cabinet (11a) to connect the cables (14) to terminals of the device body (11). The conductive cloth (15) is attached to the opening (12) and electrically connected to the shielded cabinet (11a) in such a way that the conductive cloth (15) deforms to open/close the opening (12). The conductive cloth (15) has plural vertical slits (15a) through which the cables (14) can pass. The lower side of the cloth (15) is not fixed. A plurality of conductive cloths (15) may be superposed. The lower open end may be vertically long enough to wrap the cable (14).

Abstract translation: 一种减少从电子设备的电缆接收开口辐射的电磁波的方法，不管电缆的数量如何，都容易提高电磁波屏蔽效果，并且有助于电缆连接/断开。 提供软电磁屏蔽导电布（15）以完全覆盖开口（12）。 开口（12）形成在机壳（11a）中，以将电缆（14）连接到装置主体（11）的端子。 导电布（15）安装在开口（12）上并与导电布（15）变形以打开/关闭开口（12）的方式电连接到屏蔽柜（11a）。 导电布（15）具有多个垂直狭缝（15a），电缆（14）可以通过该垂直狭缝。 布（15）的下侧不固定。 多个导电布（15）可以重叠。 下开口端可以垂直地长到足以缠绕电缆（14）。

公开(公告)号：WO1998019395A1

公开(公告)日：1998-05-07

申请号：PCT/US1996017197

申请日：1996-10-28

Applicant: ADVANTEST CORPORATION ,  ADVANTEST AMERICA, INC. ,  OKAYASU, Toshiyuki ,  SEKINO, Takashi

Inventor： ADVANTEST CORPORATION ,  ADVANTEST AMERICA, INC.

IPC: H03H11/26

CPC classification number: H03K5/13 ,  H03H11/265

Abstract: A delay time control circuit controls delay times without a significant increase of power consumption or circuit components. The delay time control circuit for controlling delay times in a logic circuit (13) includes a delay circuit (10) having a plurality of serially connected gates, a pulse signal (A1) supplied to the delay circuit; a first group of gates (11) which generates a reset pulse based on the pulse signal, a second group of gates (12) which generates a set pulse based on the pulse signal, a delay-duty converter (14) which is driven by the set and reset pulses, an integrator (15) which integrates an output signal of the delay-duty converter to produce an average voltage indicating a duty cycle of the output signal, a first delay time control voltage generator (16) which compares the average voltage and a reference voltage (17) indicating a delay time for the logic circuit and generates a first control voltage which is applied to the logic circuit, and a second delay time control voltage generator (18) which receives the first control voltage and generates a second control voltage which is symmetrical to the first control voltage and is applied to the logic circuit.

Abstract translation: 延迟时间控制电路控制延迟时间，而不会显着增加功耗或电路组件。 用于控制逻辑电路（13）中的延迟时间的延迟时间控制电路包括具有多个串联的门的延迟电路（10），提供给延迟电路的脉冲信号（A1） 基于脉冲信号产生复位脉冲的第一组门（11）;基于脉冲信号产生设定脉冲的第二组门（12）;延迟占空比变换器（14），由第 所述置位和复位脉冲，积分器（15），其积分所述延迟占空比转换器的输出信号以产生指示所述输出信号的占空比的平均电压;第一延迟时间控制电压发生器（16），其将所述平均值 电压和参考电压（17），其指示逻辑电路的延迟时间，并产生施加到逻辑电路的第一控制电压;以及第二延迟时间控制电压发生器（18），其接收第一控制电压并产生 第二控制电压与第一控制电压对称并被施加到逻辑电路。

公开(公告)号：WO1998018301A1

公开(公告)日：1998-04-30

申请号：PCT/JP1997003715

申请日：1997-10-15

Applicant: ADVANTEST CORPORATION ,  OKAYASU, Toshiyuki

Inventor： ADVANTEST CORPORATION

IPC: H05K01/02

CPC classification number: G02B6/3897 ,  G02B6/2817 ,  G02B6/3612 ,  G02B6/3809 ,  G02B6/4214 ,  G02B6/43 ,  H05K1/0274

Abstract: An optical fiber buried layer in which an optical fiber is buried is provided in part of the layers of an electrical wiring board constituting a mother board on which an electric circuit is mounted. A hole is made in the surface of the buried layer to expose one end of the buried optical fiber. A reflective face having a 45 DEG inclination is provided on the exposed end of the optical fiber to reflect light to be emitted from the optical fiber in a direction perpendicular to the board plane of the wiring board. The reflected light enters the end face of an optical fiber of a daughter board. Light emitted from the optical fiber end face of the daughter board is reflected by the 45 DEG reflective face and enters the optical fiber in the buried layer.

Abstract translation: 在构成安装有电路的母板的电气布线板的一部分层中设置有埋入光纤的光纤掩埋层。 在掩埋层的表面上形成一个孔，以露出掩埋光纤的一端。 在光纤的露出端设有倾斜45度的反射面，以反射与光纤垂直的布线板的平面方向从光纤射出的光。 反射光进入子板的光纤的端面。 从子板的光纤端面发射的光被45°反射面反射，并进入掩埋层的光纤。

公开(公告)号：WO1998014954A1

公开(公告)日：1998-04-09

申请号：PCT/JP1997003464

申请日：1997-09-29

Applicant: ADVANTEST CORPORATION ,  TAKANO, Kazuo

Inventor： ADVANTEST CORPORATION

IPC: G11C29/00

CPC classification number: G11C29/56 ,  G01R31/31935

Abstract: The circuit construction of a memory tester having a mask pattern memory is simplified. Mask pattern data read out of the mask pattern memory (11) are, without being converted into a bit arrangement corresponding to the arrangement of the terminals of a memory (200) under test, supplied directly to a masking circuit (113). Provisional fail data of the bit arrangement are given from a logic comparator (107) to a fail data selector (108) which controls the flow of the fail data whose arrangement is converted into a bit arrangement in order of weighting and supplies the fail data to the masking circuit, by which the writing into a defect analysis memory (109) is masked.

Abstract translation: 具有掩模图形存储器的存储器测试器的电路结构被简化。 从掩模图形存储器（11）中读出的掩模图案数据不被转换为与被测试的存储器（200）的端子的布置相对应的位布置，直接提供给屏蔽电路（113）。 比特排列的临时故障数据从逻辑比较器（107）被提供给故障数据选择器（108），故障数据选择器（108）控制按照加权顺序将其排列转换成比特排列的故障数据的流程，并将故障数据提供给 屏蔽电路，通过该屏蔽电路对缺陷分析存储器（109）的写入被屏蔽。

公开(公告)号：WO1997046071A1

公开(公告)日：1997-12-04

申请号：PCT/JP1997001810

申请日：1997-05-28

Applicant: ADVANTEST CORPORATION ,  FURUTA, Katsunobu

Inventor： ADVANTEST CORPORATION

IPC: H05K13/08

CPC classification number: H05K13/02 ,  H05K13/0408 ,  H05K13/08

Abstract: This detector is provided with a suction transfer arm (12) for vacuum sucking an object material (11) at a nozzle bore and transferring the material in the horizontal and vertical directions. On the rear side of the portion of a stage (13) on which the material (11) to be sucked is placed, an upwardly directed light-emitting sensor (14) is provided. The portion of the stage on which the material (11) to be sucked is placed is provided with a through hole by which the upward rays of light-emitting sensor (14) is not shut off. At an inner part of the nozzle bore of the suction transfer arm (12), a downwardly directed light receiving sensor (15) for receiving the rays of light from the light-emitting sensor (14) is provided.

Abstract translation: 该检测器设置有用于在喷嘴孔处真空吸取物体（11）并在水平和垂直方向上传送材料的抽吸传递臂（12）。 在其上放置待吸收材料（11）的台（13）的部分的后侧设置有向上指示的发光传感器（14）。 被放置的材料（11）所在的台阶部分设置有通孔，通过该通孔，向上的发光传感器（14）不被切断。 在抽吸传送臂（12）的喷嘴孔的内部，设置有用于接收来自发光传感器（14）的光线的向下定向的光接收传感器（15）。

公开(公告)号：WO1997045869A1

公开(公告)日：1997-12-04

申请号：PCT/JP1997001809

申请日：1997-05-28

Applicant: ADVANTEST CORPORATION ,  MATSUMURA, Shigeru

Inventor： ADVANTEST CORPORATION

IPC: H01L23/32

CPC classification number: H05K7/1061 ,  G01R1/0483

Abstract: A semiconductor package (11) has a substrate (12) which is mounted with a semiconductor chip on one surface and numerous external terminals (14) arranged at prescribed pitches on the other surface. Positioning holes (13) are formed at two or more desired locations of the substrate (12) so as to ensure the dimensional accuracy between the holes and one arbitrary external terminal (14a).

Abstract translation: 半导体封装（11）具有在一个表面上安装有半导体芯片的基板（12）和在另一表面上以规定间距布置的许多外部端子（14）。 在基板（12）的两个以上的期望位置处形成定位孔（13），以确保孔与一个任意的外部端子（14a）之间的尺寸精度。

公开(公告)号：WO1997034299A1

公开(公告)日：1997-09-18

申请号：PCT/JP1996000597

申请日：1996-03-11

Applicant: ADVANTEST CORPORATION ,  KANAI, Junichi

Inventor： ADVANTEST CORPORATION

IPC: G11C29/00

CPC classification number: G11C29/028 ,  G11C16/04 ,  G11C29/26 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56

Abstract: A semiconductor testing device with a rewrite controller, having a function to conduct simultaneous measurement of a rewritable semiconductor memory such as a flash memory, and capable of controlling rewrite of one page at a time thereby to shorten the testing time. The semiconductor testing device is provided with a holding means (5) which detects fail information during the rewrite of one page from the output signal of an inspecting circuit (1) and holds the information, judging means (11) which judges whether or not any of the devices to be measured fails when one page rewrite is completed, and a rewrite control section (100) which outputs the output signal of the judging means or flip-flop (11) as a rewrite inhibiting signal (102). A plurality of such rewrite control sections (100, 200, 300) may be provided depending on the number of devices.

Abstract translation: 具有重写控制器的半导体测试装置，其具有进行诸如闪存等可重写半导体存储器的同时测量的功能，并且能够一次控制一页的重写，从而缩短测试时间。 半导体测试装置设置有保持装置（5），其在从检查电路（1）的输出信号重写一页期间检测失败信息，并保存该信息，判断装置（11）判断是否有任何 当完成一页重写时要测量的器件失败;以及重写控制部分（100），其输出判断装置或触发器（11）的输出信号作为重写禁止信号（102）。 可以根据设备的数量来提供多个这样的重写控制部分（100,200,300）。

公开(公告)号：WO1997011381A1

公开(公告)日：1997-03-27

申请号：PCT/JP1996002731

申请日：1996-09-20

Applicant: ADVANTEST CORPORATION ,  TAKAHASHI, Kouji

Inventor： ADVANTEST CORPORATION

IPC: G01R31/28

CPC classification number: G11C29/56 ,  G01R31/31935 ,  G11C29/44

Abstract: A memory tester which judges quickly whether or not a faulty IC memory can be repaired. A fail cell (1) receives a fail signal from a logic comparator (14) and an address signal for receiving a fail signal from a pattern generator (23) and stores only the faulty address of the IC memory, and is constituted of an address holding register (3), an address comparator (5), and a controller (8). Using a fail cell array (2) in which a plurality of fail cells are cascade-connected, only fail addresses among the data used for making a fail map are stored. Consequently the time taken to read the fail addresses from the fail cell array and to send them to an operation section (15) is shortened.

Abstract translation: 一种快速判断故障IC存储器是否可以被修复的存储器测试器。 故障单元（1）接收来自逻辑比较器（14）的失败信号和用于从模式发生器（23）接收失败信号的地址信号，并且仅存储IC存储器的故障地址，并且由地址 保持寄存器（3），地址比较器（5）和控制器（8）。 使用其中多个故障单元级联连接的故障单元阵列（2），仅存储用于制作失效映射的数据中的故障地址。 因此，从故障单元阵列读取失败地址并将其发送到操作部分（15）所花费的时间被缩短。

公开(公告)号：WO1997004327A1

公开(公告)日：1997-02-06

申请号：PCT/JP1995001438

申请日：1995-07-20

Applicant: ADVANTEST CORPORATION ,  TSURUKI, Yasutaka

Inventor： ADVANTEST CORPORATION

IPC: G01R31/28

CPC classification number: G01R31/31709 ,  G01R31/31922 ,  H03L7/06

Abstract: A semiconductor tester which fetches a clock signal generated from a device to be tested, stabilizes the clock signal by removing jitter components, and uses the stabilized clock signal to operate the device. The tester includes a frequency divider A (11) which receives the clock signal (21) from the device to be tested, a phase detecting circuit (12), a loop filter (13), a VCO (14), a frequency divider B (16), a test period generator (15), and an interleave circuit (18). The clock signal outputted from the VCO (14) is inputted to the test period generator (15) to produce a test period signal (23), which is distributed to internal circuits of the device and, at the same time, is fed back to the phase detector (12) through the frequency divider B (16).

Abstract translation: 取得要测试的器件产生的时钟信号的半导体测试器通过去除抖动分量来稳定时钟信号，并使用稳定的时钟信号来操作器件。 测试器包括从被测器件接收时钟信号（21）的分频器A（11），相位检测电路（12），环路滤波器（13），VCO（14），分频器B （16），测试周期发生器（15）和交错电路（18）。 从VCO（14）输出的时钟信号被输入到测试周期发生器（15），以产生测试周期信号（23），该测试周期信号被分配到该器件的内部电路，同时被反馈到 相位检测器（12）通过分频器B（16）。

公开(公告)号：WO1996023363A1

公开(公告)日：1996-08-01

申请号：PCT/JP1996000110

申请日：1996-01-23

Applicant: ADVANTEST CORPORATION ,  KITAYOSHI, Hitoshi

Inventor： ADVANTEST CORPORATION

IPC: H04B01/10

CPC classification number: H01Q3/08

Abstract: Radio waves having frequencies of f1 and f2 are radiated in an area where a wireless LAN is to be set up, the radio waves f1 and f2 are separately received with an antenna which scans the surface to be observed and a fixed antenna, and their radio wave holograms are produced. Then radio wave images separated for each path are formed from the holograms, and the amplitude and delay of each path are found by finding the difference between the radio wave images. The propagation time response function x(t) of each path is found from the amplitude, delay, and the directional characteristics of the antennas and the real part and imaginary part of the function are convoluted in a modulated carrier signal y(t). Then the real and imaginary parts are respectively multiplied by the in-phase component Rf and the orthogonal component Rf* of a non-modulated carrier. Finally, a demodulated base-band signal gamma (t) is obtained by adding both products to each other. The radio wave time lag of each secondary radio wave image with respect to a primary radio wave source is found and the radio wave images are rearranged in an absolute three-dimensional coordinate system by using the time lags. Then the intensity of the radio waves at an arbitrary position in the absolute coordinate system is found by combining radio waves from each radio wave image and the mean value and standard deviation of the delays are found from the time lags and intensity attenuation corresponding to the distance to each radio wave image.

Abstract translation: 具有f1和f2频率的无线电波被辐射到要建立无线LAN的区域中，无线电波f1和f2被分别接收到扫描待观察表面的天线和固定天线，并且它们的无线电 产生波全息图。 然后，从全息图形成每个路径分离的无线电波图像，通过找到无线电波图像之间的差异来找出每个路径的振幅和延迟。 每个路径的传播时间响应函数x（t）从天线的幅度，延迟和方向特性中找出，并且函数的实部和虚部被卷积在调制载波信号y（t）中。 然后将实部和虚部分别乘以非调制载波的同相分量Rf和正交分量Rf *。 最后，通过将两个乘积彼此相加来获得解调的基带信号γ（t）。 找到相对于主无线电波源的每个次级无线电波图像的无线电波时滞，并且通过使用时间滞后在绝对三维坐标系中重新排列无线电波图像。 然后，通过组合来自每个无线电波图像的无线电波来求出绝对坐标系中的任意位置处的无线电波的强度，并且从与距离对应的时间滞后和强度衰减中找出延迟的平均值和标准偏差 到每个无线电波图像。